US 5,347,232 A · Phase locked loop clock generator

Abstract

A phase locked loop (PLL) is disclosed, which produces a source clock signal which has a frequency twice that of a reference clock signal fed from the outside and is in synchronism with a reference clock signal. A timer counts pulses of a reference clock signal in order to measure time corresponding to the lock-in time of the PLL and delivers a count completion signal when the value of counting reaches a predetermined value. A start controller is in control of a clock buffer so that, after a count completion signal is delivered, the clock buffer starts feeding a source clock signal to a load circuit as an internal clock signal, in synchronism with a reference clock signal. A stop controller is also in control of the clock buffer so that, when a clock stop request signal becomes asserted, the clock buffer stops feeding an internal clock signal, in synchronism with a reference clock signal.

Claims19

Dependent claims

A clock generator for feeding as a source clock signal an internal clock signal in synchronism with an external clock signal serving as a reference clock signal to a load circuit, said clock generator comprising:

a clock signal generation means for generating the source clock signal, having an initial phase, to be input to said load circuit, said clock signal generation means further adjusting the initial phase of said source clock signal generated to another phase causing the source clock signal to be synchronous with the reference clock signal;
and
a clock signal propagation control means for controlling the propagation of the source clock signal delivered from said clock signal generation means by preventing said source clock signal as the internal clock signal from being outputted to said load circuit unless the source clock signal can be fed in synchronism with said reference clock signal.

a clock signal generation means for generating said source clock signal, having an initial phase, to be output to said load circuit, said clock signal generation means further adjusting the phase of said source clock signal generated to be synchronous with said reference clock signal,
a time measurement means for measuring a length of time necessary for said source clock signal delivered from said clock generation means to become synchronous with said reference cloak signal;
and
a clock signal transmission control means for preventing transmission of said source clock signal as an internal clock signal to said load circuit until said time measurement means completes measurement of the time necessary for said source and reference clock signals to be synchronous.

1 more element

a clock signal generation means for generating a source clock signal having an initial phase, said clock signal generation means further adjusting the phase of said source clock signal generated to another phase to be synchronous with a reference clock signal,
a synchronization detection means for detecting the synchronization between said source clock signal produced by said clock generation means and said reference clock signal input to said clock signal generation means;
and
a clock signal transmission control means for preventing transmission of said source clock signals delivered from said clock signal generation means to said load circuit until said synchronization detection means detects synchronization between said source clock signal produced by said clock generation means and said reference clock signal input to said clock generation means.

1 more element

Dependencies are inferred from the claim text.

Phase locked loop clock generator

Life of this patent

Phase locked loop clock generator

Life of this patent

Abstract

Claims19