Clock phase adjustment between duplicated clock circuits

An apparatus for adjusting phase of the first timing signals generated by a first timing unit to match phase of second timing signals generated by a second timing unit, comprising:

• means in the first timing unit for repetitively generating a first signal after a first predetermined number of first timing signals of the first timing unit;
• means in the second timing unit for repetitively generating a second signal after a second predetermined number of second timing signals of the second timing unit where the first and second predetermined numbers are equal;
• means in the first timing unit for counting at a fixed rate in response to the first signal;
• means for transmitting the second signal to the counter and the transmitting means being adjusted to cause a delay resulting in an integer count of the counting means;
• the counting means further responsive to the second signal to stop counting;
• and
• means in the first timing unit for modifying the phase of the first timing unit in response to the contents of the counting means and the integer count due to the delay of the transmission means for adjusting the phase of the first timing unit upon the counting means stopping.

A method for adjusting phase of first timing signals generated by a first clock circuit, the method comprising the steps of:

• counting at a fixed rate in response to being started by an internal signal repetitively generated by the first clock circuit after generation of a first predetermined number of first timing signals by the first clock circuit;
• repetitively generating by a second clock circuit an external signal after generation of a second predetermined number of second timing signals by the second clock circuit where the first and second predetermined numbers are equal;
• transmitting the external signal to the counter and the transmitting step being adjusted to cause a delay resulting in an integer count of the counting step;
• the counting step further responsive to receipt of the external signal by the first clock circuit to stop counting;
• and
• modifying the phase of the first timing signals of the first clock circuit in response to the number generated by the step of counting and the integer count due to the delay of the transmission step for adjusting the phase of the clock circuit upon the counting being stopped.

A method for adjusting phase of first timing signals generated by a first timing unit to match phase of second timing signals generated by a second timing unit, the method comprising the steps of:

• repetitively generating by the first timing unit a first signal after a first predetermined number of first timing signals of the first timing unit;
• repetitively generating by the second timing unit a second signal after a second predetermined number of second timing signals of the second timing unit where the first and second predetermined numbers are equal;
• counting by the first timing unit at a fixed rate in response to being started by the first signal;
• transmitting the second signal to the counter and the transmitting step being adjusted to cause a delay resulting in an integer count of the counting step;
• the counting step further in response to the second signal stops counting;
• and
• modifying by the first timing unit the phase of the first timing unit in response to results of the counting step and the integer count due to the delay of the transmission step for adjusting the phase of the first timing unit upon the counting step stopping.