Dual receiver edge-triggered digital signal level detection system
AssigneeTexas Instruments Incorporated
InventorsMichael C. Stephens, Jr., Roger D. Norwood, Duy-Loan T. Le, Kenneth A. Poteet
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AssigneeTexas Instruments Incorporated
InventorsMichael C. Stephens, Jr., Roger D. Norwood, Duy-Loan T. Le, Kenneth A. Poteet
Estimating the term…
Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.
A level detection system receiving two input signals to indicate one or another logic state of the first input signal at the transition of the second input signal from an inactive state to an active state, the system comprising:
A process of indicating one or another logic state of a first input signal at the transition of a second input signal from an inactive state to an active state, the process comprising:
Dependencies are inferred from the claim text.