CMOS semiconductor logic circuit with multiple input gates

A semiconductor logic circuit comprising:

• first and second multiple-input gate circuits each including first second and third inputs, a series circuit including first, second and third serially connected transistors of one conductivity type, and first, second and third transistors of a different conductivity type connected to said series circuit;
• first, second and third input pins;
• a control electrode of each of said first, second and third serially connected transistors, of sad first multiple-input gate circuit, being connected to a respective one of said first, second, and third input pins;
• an output pin connected to a connection, between said series circuit and said first, second and third transistors of said different conductivity type, of each of said first and second multiple-input gate circuits;
• and
• a control electrode of each of said first, second and third serially connected transistors, of said second multiple-input gate circuit, being connected to one of said third, second, and first input pins, respectively.

A semiconductor logic circuit, disposed between a voltage supply and a ground, comprising:

• a plurality of multi-input circuits;
• a plurality of inputs connected to each of said multi-input circuits;
• an output node;
• said plurality of multi-input circuits including a plurality of transistors in series being one of p type and n type;
• said plurality of multi-input circuits including a plurality of transistors in parallel being the other of p type and n type;
• said plurality of transistors in series being disposed between said output node and one of said voltage supply and said ground;
• said plurality of transistors in parallel being disposed between said output node and another of said voltage supply and said ground;
• and
• said plurality of inputs being uniquely connected to each of said plurality of multi-input circuits, wherein each k.sup.th transistor, of said plurality of transistors in series of each of said multi-input circuits, is connected to a different one of said plurality of inputs.

A semiconductor logic circuit disposed between a voltage supply and a ground, comprising:

• a plurality of multi-input circuits having k inputs and an output node;
• said plurality of multi-input circuits including k transistor in series being one of p type and n type;
• said plurality of multi-input circuits including k transistors in parallel being the other of p type and n type;
• said k transistors in series being disposed between said output node and one of said voltage supply and said ground;
• said k transistors in parallel being disposed between said output node and another of said voltage supply and said ground;
• and
• each of said k inputs being uniquely connected to each of said plurality of multi-input circuits, wherein each x.sup.th transistor, of said k transistors in series of each of said multi-input circuits, is connected to a different one of said k inputs, were x is between 1 and k.

A logic circuit for receiving a plurality, n, of inputs and producing an output, comprising:

• at least first and second input circuits;
• each of said first and second input circuits including n parallel transistors connected in parallel between a first reference voltage and said output;
• each of said at least first and second input circuits including n series transistors connected in series between said output and a second reference voltage;
• all of said n parallel transistors being of a first conductivity type;
• all of said n series transistors being of a second conductivity type;
• a first of said n inputs being connected to a one of said n serial transistors situated closest to sad second reference voltage in said first input circuit, and to a one of said n serial transistors further from said second reference voltage in said second input circuit;
• and
• a second of said n inputs being connected a second of said n serial transistors situated further from said second reference voltage in said first input circuit, and to a second one of said n serial transistors closest to said second reference voltage in said second input circuit.