Semiconductor input/output circuits operating at different power supply voltages

A semiconductor integrated circuit device comprising:

• a semiconductor substrate;
• a plurality of interface terminals on a peripheral portion of said semiconductor substrate;
• a main logic circuit portion on said semiconductor substrate;
• a plurality of well regions of a conductivity type different from that of said semiconductor substrate, between said terminals and said main logic circuit portion, at least one of said well regions being biased at a potential different from that of said semiconductor substrate;
• and
• a plurality of interface circuits each having a MOSFET in one of said well regions, said MOSFET having a first terminal connected to one of said interface terminals, and a second terminal connected to said main logic circuit portion, and having a CMOS structure,
• wherein said well regions extend along each side of said semiconductor substrate, and said well region along with each side of said semiconductor substrate is joined to said well region formed along each adjacent side to form an annular region extending along the peripheral portion of said semiconductor substrate, and a plurality of annular well regions similar to said annular region are formed.

A semiconductor integrated circuit device comprising:

• a semiconductor substrate;
• a plurality of interface terminals on a peripheral portion of said semiconductor substrate;
• a main logic circuit portion on said semiconductor or substrate;
• a plurality of well regions of a conductivity type different from that of said semiconductor substrate, between said interface terminals and said main logic circuit portion, at least one of said well regions being biased at a potential different from that of said semiconductor substrate;
• and
• a plurality of interface circuits each having a MOSFET in one of said well regions, said MOSFET having a first terminal connected to one of said interface terminals, and a second terminal connected to said main logic circuit portion, and having a CMOS structure,
• wherein said well regions extend along each side of said semiconductor substrate, each of said well regions is of an n-type when said semiconductor substrate is a p-type semiconductor, and is of a p-type when said semiconductor substrate is an n-type semiconductor, and said well region along with each side of said semiconductor substrate is joined to said well region formed along each adjacent side to form an annular region extending along the peripheral portion of said semiconductor substrate, and a plurality of annular well regions similar to said annular region are formed.

A semiconductor integrated circuit device comprising:

• a semiconductor substrate;
• a plurality of interface terminals on a peripheral portion of said semiconductor substrate;
• a main logic circuit portion on said semiconductor substrate;
• a plurality of well regions of a conductivity type different from that of said semiconductor substrate, between said interface terminals and said main logic circuit portion, including a first well region between an interface terminal and said main logic circuit portion, and a second well region between the interface terminal and the first well region, at least one of said well regions being biased at a potential different from that of said semiconductor substrate;
• and
• plurality of interface circuits each having a MOSFET in one of said well regions, said MOSFET having a first terminal connected to one of said interface terminals, and a second terminal connected to said main logic circuit portion, and having a MOS structure,
• wherein said well regions extend along each side of said semiconductor substrate.