Pad arrangement for a semiconductor device

A semiconductor device, comprising:

• a rectangular semiconductor chip having an integrated circuit;
• a plurality of voltage stress examination pads on said semiconductor chip for receiving a stress examination signal to be applied to said integrated circuit, said voltage stress examination pads including groups of pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said rectangular semiconductor chip, and a second pad of each group is arranged adjacent to a second side of said rectangular semiconductor chip, said second side being opposite said first side.

A semiconductor device, comprising:

• semiconductor chips arranged in rows and columns on a semiconductor wafer, each semiconductor chip including an integrated circuit;
• a plurality of pads on each semiconductor chip connected to the corresponding integrated circuit, each semiconductor chip including a group of pads, wherein the pads of each group are connected to each other, a first pad of said group is arranged adjacent to a first side of said semiconductor chip, and a second pad of said group is arranged adjacent to a second side of said semiconductor chip, said second side being opposite said first side.

A system for simultaneously subjecting a plurality of integrated circuits in semiconductor chip regions to a voltage stress examination, said semiconductor chip regions arranged in rows and columns on a semiconductor wafer and each semiconductor chip region having groups of voltage stress examination pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said each semiconductor chip region, and a second pad of each group is arranged on a second side of said each semiconductor chip region, said second side being opposite said first side, wherein said system includes a probe card having probes extending from opposed first and second sides thereof, the probes extending from the first side being arranged to contact, during the voltage stress examination, voltage examination pads adjacent to a side of a first semiconductor region in a first row and voltage examination pads adjacent to a side of a second semiconductor chip region in a second row, wherein said side of said second semiconductor chip region is adjacent to said side of said first semiconductor region.

A semiconductor device, comprising:

• a semiconductor chip including an integrated circuit;
• a plurality of voltage stress examination pads on said semiconductor chip for receiving a stress examination signal to be applied to said integrated circuit, said voltage stress examination pads including groups of pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said semiconductor chip, and a second pad of each group is arranged adjacent to a second side of said semiconductor chip.