Method of making a groove structure for isolation between elements comprising a GTO thyristor
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorFutoshi Tokunoh
Life of this patent
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Abstract
A semiconductor structure comprises a gate-turn-off thyristor region (GR) and a diode region (DR) with an isolation area (SR) therebetween. The isolation area is provided with a multistage groove (30) having step structures (34,35). The multistage groove is formed through a two-stage etching process, and over-etched regions in the bottom corners of the multistage groove are relatively shallow ones. This structure is effective for increasing the breakdown voltage of the semiconductor structure and isolations between the gate-turn-off thyristor region and the diode region.
Claims12
A method of manufacturing a semiconductor device, comprising the steps of:
- (a) forming in a semiconductor body first and second semiconductor element structures disposed with an area therebetween in a direction parallel to a major surface of said semiconductor body;
- (b) selectively etching a part of said major surface of said semiconductor body located in said area to form a groove having a width within said area;
- and
- (c) selectively etching said major surface of said semiconductor body in a range including said groove and wider than said groove to form a multistage groove having a depth increasing stepwise in series toward the center thereof.
Dependencies are inferred from the claim text.