Method of fabricating a parallel processor package
AssigneeInternational Business Machines Corporation
InventorsHarold Kohn, Donald J. Lazzarini
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AssigneeInternational Business Machines Corporation
InventorsHarold Kohn, Donald J. Lazzarini
Estimating the term…
Disclosed is a method for manufacturing a stacked circuitized flex structure. The structure is a laminate for Z-axis communication within a parallel processor. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Z-axis circuitization is carried out by providing vias and through holes in individual circuitized flex strips. These vias and through holes are circuited and plated. This is followed by filling the vias and through holes with solder and forming solder bumps at the tops and bottoms of the vias and through holes. A sticker sheet with clearance holes for the solder bumps is provided, and a plurality of the circuitized flex strips are laid up for lamination to form a stack of circuitized flexible strips. Lamination is carried out at elevated pressure and temperature to crush the solder bumps, bond, and homogenize solder bump material and fuse the sticker sheets. Next, the stack is cooled to solidify the homogenized solder bump material.
A method of fabricating a parallel processor structure having a plurality of processor integrated circuit chips, and a plurality of memory integrated circuit chips, with signal interconnection circuitization means therebetween, wherein
Dependencies are inferred from the claim text.