US 5,345,582 AGranted

Failure detection for instruction processor associative cache memories

AssigneeUnisys Corporation

InventorKenichi Tsuchiya

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Abstract

A system for detecting failures in a cache memory stores data words that may represent instructions or operands in plurality of blocks. The data words are divided into a plurality of data bit groups. A tag memory is associated with each block of data words in the cache memory. Storage in the cache memory is directed by block address bits, and storage in the tag memory is directed by tag address bits. A first parity generator is coupled to the cache memory which generates address parity bits selected from block and tag address bits. A second parity generator provides data parity bits for each group of the data word bits. These two parity bits are combined and are stored along with the bit groups of the associated data word. Upon read-out of a data word, the stored combined parity bits are compared with parity bits that were generated from the selected address bits and data bits and error indication occurs when a parity error results.

Claims2

Dependent claims

A method of detecting failures in a cache memory which stores multiple bit input data words in groups of data bits organized into a plurality of blocks which are operatively associated with a tag memory and which stores a tag portion of memory address bits that corresponds to each block of the data words that are currently stored in said cache memory, wherein a multiplexor means is coupled to said tag and cache memories for controlling the reading from, and the writing into, said cache memory in accordance with tag address bits that are stored in said tag memory, data word storage in said cache memory is directed by block address bits, and tag bit storage in said tag memory is directed by tag address bits comprising the steps of:

(a) generating, upon writing into said cache memory a plurality of address parity bits from a plurality of said memory address bits selected from the block address bit groups and the tag address bit groups that are associated with each address that is selected,
(b) generating at least one data parity bit for each group of data bits of said multiple bit input data words,
(c) forming a combined parity bit for each of said groups of data bits and at least one of said address parity bits,
(d) storing said combined parity bits in the blocks in said cache memory that are associated with the groups of said data bits from which said parity bits were derived,
(e) storing said group of data bits along with the associated combined parity bits in said cache memory,
(f) determining if said tag address bits represent a set of words that are stored in said cache memory, and then only if they do represent such a set of words:
(1) reading a data word from said cache memory at a selected read address,
(2) generating at least one said address parity bit from the cache and tag address bits that are associated with each group of data bits read from the selected read address,
(3) comparing a combined parity bit of the selected read address and the data bits read out to the combined stored parity bit that was generated upon read out of a stored group of data bits which corresponded to the address selected for readout, and
(4) generating indications of parity errors when such comparison indicates that such errors have occurred.

7 more elements

A failure detection system for detecting failures in a cache memory which stores multiple bit input data words in location in a plurality of blocks that are specified by memory address bits, and which is operatively associated with a tag memory which stores a portion of said memory address bits of said data words that are currently retained in said cache memory, comprising:

control means coupled to said tag memory and to said cache memory for controlling the reading of bits from, and the writing of bits into, said cache memory in accordance with bits stored in said tag memory,
(a) first means coupled to said cache memory for generating upon writing into said cache memory at least one address parity bit selected from at least one of the block address bit groups and one of the tag address bit groups that are associated with each address that is selected,
(b) second means coupled to said control means for generating at least one data parity bit from said multiple bit input data words for each group of data bits that are stored in each of said blocks,
(c) third means for combining said parity bits from each of group of data bits with the parity bit that is derived from the address bits that are associated with the same group of data bits,
(d) fourth means for storing said combined parity bits in the blocks that are associated with the groups of data word bits from which said parity bits were derived,
(e) fifth means for storing said data bits along with the associated combined parity bits,
(f) sixth means for determining if said tag address bit represents a block stored in said cache memory,
(g) seventh means for generating, upon reading from said cache memory, said at least one address parity bit for each set of cache and tag address bits for each selected address to provide corresponding address parity bits,
(h) eighth means for comparing each read-out group of data bits and associated stored combined parity bits with the associated one of said address parity bits that were generated upon read out of the associated store group of data bits and the corresponding combined parity bit from said cache memory, and
(i) ninth means for receiving said corresponding address parity bits and said corresponding combined parity bit and for generating an indication of a parity error when one occurs in any of said groups of data bits only if said tag address bits are determined by said sixth means to represent a block stored in said cache memory.

7 more elements

Dependencies are inferred from the claim text.