A multiprocessor computer system including cache memories for processor access to data storage, comprising:
- m-dimensional buses, each bus bearing an identifying index, each said identifying index being a bus m-tuple containing an ordered list of integers of which exactly one integer is zero;
- a plurality of units bearing m index numbers for identification, each said m index numbers forming a unit m-tuple containing an ordered list of integers all of which integers are non-zero,
- each said unit including a processor and associated cache memory for storing data, each said processor being able to assert read and write requests for data stored in any said cache memory in any said unit;
- and
- a plurality of gateway means, each said gateway means;
- (i) coupled to an intersection of said m-dimensional buses for facilitating retrieval of data stored in a said associated cache memory upon request of a said processor associated with a said gateway means and said cache in a said unit, said m-dimensional buses meeting at said intersection being those buses whose said bus m-tuple is identical to said unit m-tuple after replacing an integer in the said unit m-tuple with integer zero,
- (ii) including queuing means for synchronizing requests from said processors,
- (iii) including coupling means for enabling each said processor to be coupled simultaneously to each other said processor in said system providing that processors so coupled are associated with gateway means coupled to a same said m-dimensional bus,
- (iv) including means for governing read and write requests from a said processor, said means for governing performing the following functions in cooperation with a said processor in a said unit asserting a request:
- (a) if requested data is within said unit asserting a request, the request is deemed satisfied,
- (b) if requested data is not within said unit asserting a request, said unit asserting a request is selectively coupled by said gateway means to all other said units bearing at least one index identical to an index of said requesting unit,
- (c) if step (b) results in said unit asserting a request being coupled by a said gateway to a said unit whose associated said cache memory includes the requested data, the request is deemed satisfied,
- (d) the requested data is added to said associated cache of said unit asserting a request upon the request satisfaction, and
- (e) if step (b) does not result in said unit asserting a request initially being coupled by a said gateway means to a said unit whose associated said cache memory includes the requested data, at least one said unit selectively coupled in step (b) re-asserts said request upon behalf of said unit asserting said request initially whereupon steps (b), (c), (d) and (e) are repeated until the request so re-asserted is deemed satisfied, and
- (f) the requested data is added to said associated caches of said units re-asserting the request in accordance with step (e) and to said associated cache of said unit asserting the request initially upon the request satisfaction.