Dram refresh controller with improved bus arbitration scheme

In a computer system having a central processing unit (CPU), a dynamic random access memory (DRAM), first control means for controlling a direct memory access (DMA) cycle, second control means for controlling a local DRAM access, third control means for controlling an advanced technology (AT) bus access, and a bus network interconnecting said CPU, DRAM, first, second and third control means, an apparatus for refreshing said DRAM comprising:

• hidden refresh latch means, having an input coupled to said bus network, for storing a signal indicating a hidden refresh mode;
• timing means for periodically generating a refresh request signal at an output;
• arbitration means, having a first input coupled to said timing means output and a second input coupled to an output of said latch means, for providing a hidden refresh enable signal only in said hidden refresh mode and when there is no memory access by said AT, DRAM and DMA control means, said arbitration means further including:
• counting means for arbitrating between a simultaneous DMA request and refresh request, said counting means providing a sequential count to enable one of said refresh and said DMA request when a corresponding count is reached;
• and
• enabling means coupled to an output of said counting means for providing said refresh enable signal only when said enabling means receives a not busy signal from said DMA and said DRAM control means;
• refresh counter means, coupled to said arbitration means and responsive to said hidden refresh enable signal, for providing a refresh end signal after a predetermined count sufficient for a refresh of said DRAM;
• and
• means, coupled to said AT, DRAM and DMA control means, for disabling said AT, DRAM and DMA control means in response to said hidden refresh enable signal, and for re-enabling said AT, DRAM and DMA control means in response to said refresh end signal.