Instruction fetch circuit which allows for independent decoding and execution of instructions

An instruction fetch circuit including:

• first shift register means for storing a digital word having first and second bytes, said first shift register means providing first and second outputs of said first and second bytes respectively;
• first multiplexer means for selecting and storing either of said first and second outputs of said first shift register means and providing a first intermediate output corresponding thereto the first multiplexer means including;
• second multiplexer means for selecting and storing either of said first or second outputs of said first shift register means or said first intermediate output and providing a second intermediate output corresponding thereto;
• third multiplexer means for selecting and storing either of said first or second outputs of said first register means or said first intermediate output or said second intermediate output and providing a third intermediate output corresponding thereto;
• fourth multiplexer means for selecting and storing either of said first or second outputs of said first register means or said first intermediate output or said second intermediate output or said third intermediate output and providing a fourth intermediate output corresponding thereto, said first, second, third, fourth multiplexer means each include a multiplexer connected to a shift register;
• output multiplexer means for selectively outputting either said first and second intermediate outputs or said second and third intermediate outputs, said output multiplexer means including a second and third shift register connected to a multiplexer;
• and
• instruction fetch control means for selectively activating said first shift register means and said first, second, third, fourth and output multiplexer means, and for allowing the first and second bytes of a data word to be shifted separately and allowing for a loading of a first instruction with a fetch of a next instruction.