In a computer system comprising at least one processor configured to overlap the processing of a plurality of instructions, the at least one processor having a program status word having a system mask, access key, and address space code, each of the at least one processor having a decoder, an execution unit coupled to the decoder, a queue coupled to the execution unit, and an architected register coupled to the execution unit and queue, a method for modifying the program status word with overlap instruction processing enabled comprising the steps of:
- (a) receiving a program status word modification instruction by the decoder;
- (b) processing said program status word modification instruction with overlap instruction processing enabled by the execution unit according to an unarchitected program status word contained in the queue, wherein said program status word modification instruction being processed generates a new program status word;
- (c) transferring said new program status word into the queue by a first transfer means coupled to the execution unit and the queue;
- (d) determining, by a completion detection unit coupled to the execution unit, whether said execution unit completely processes said program status word modification instruction;
- (e) transferring said new program status word from the queue to the architected register by a second transfer means coupled to the queue and the architected register in response to said execution unit completely processing said program status word modification instruction wherein the architected register stores an architected program status word, said architected program status word being said existing program status word in the at least one processor;
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- (f) discarding, by the execution unit, said new program status word from the queue in response to incomplete processing of said program status word modification instruction.