US 5,345,564 A · Serial communication peripheral integrated electronic circuit that recognizes its unique address before the entire circuit is enabled

Abstract

A peripheral integrated electronic circuit of the type having an interface for serially transferring data between it and a central processing unit ("CPU") in a computer system that employs a number of such peripheral circuits that are selectively rendered operable by the CPU, one at a time. The peripherals each include an interface that receives an initial data word from the CPU that identifies the peripheral circuit with which data is to be transferred by the CPU. Rather than all such peripherals in a computer system being powered-up in order to have their processors determine individually under software control whether they have been identified by the CPU, only a small hardwired interface circuit is so enabled. Once this interface circuit determines that the CPU desires to conduct data transfer with it, the main portion of the circuit, including its processor, is then powered-up.

Claims3

Dependent claims

In a computer system having a central processing unit ("CPU") connected in parallel with at least two peripheral units that contain unique identification codes and have internal processors, a method of activating a selected one of said at least two peripheral units to operate with the CPU, comprising the steps of:

causing the CPU to transmit one of the unique identification codes to all of said at least two peripheral units,
comparing in a hardware circuit of each of said at least two peripheral units its unique identification code with the identification code being transmitted by the CPU, said comparing step occurring without activating the internal processors in any of said at least two peripheral units,
selecting one of said at least two processing units wherein its unique identification code matches the transmitted identification code, and
activating the internal processor within the selected one of said at least two processing units by supplying a clock signal to the internal processor of the selected peripheral processing unit without activating the internal processor in any other of said at least two peripheral units.

1 more element

Dependencies are inferred from the claim text.

Serial communication peripheral integrated electronic circuit that recognizes its unique address before the entire circuit is enabled

Life of this patent

Serial communication peripheral integrated electronic circuit that recognizes its unique address before the entire circuit is enabled

Life of this patent

Abstract

Claims3