US 5,345,563 AGranted

Input/output interface for data in parallel processors

AssigneeBodenseewert Geratetechnik GmbH

InventorsChristoph Uihlein, Michael Hausing, Andreas J. Puhler

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Abstract

An input/output interface for converting between data patterns in bit-parallel and word-serial format and data patterns in word-parallel and bit-serial format. In combination with a parallel processor, the inputting and outputting rates of the data are to be increased. To this end, a three dimensionally organized memory with a three-dimensional addressing is connected to the input and/or to the output of the parallel processor. Each address is composed of three components, of which a first component represents the significance of a bit, the second component represents the running number of the word in a limited sequence of words, and the third component represents the running number of the sequence, to which the word belongs. A switching network for the control of the memory is associated with the memory. The memory is arranged to buffer an incoming data stream of bit-parallel and word-serial format. The data from the memory are applied to the parallel processor as bit-serial and word-parallel data pattern in the form of "bit planes" of identical bit addresses. Alternatively, the memory may serve to buffer a data stream provided by the parallel processor in bit-serial and word-parallel format as a sequence of "bit planes" , the data being outputted as a bit-parallel and word-serial data pattern.

Claims12

Dependent claims

An interface for converting bit-parallel and word-serial data patterns into bit-serial and word-parallel data patterns or vice versa, comprising:

a three-dimensionally organized data memory, each address in said data memory having three components, each component representative of one of each of the three dimensions of the memory;
means for receiving a preset number of successive sets of parallel bits of data to be stored in memory, the successive sets to be arranged in memory in a preset two dimensional pattern;
output means for outputting a preset number of successive sets of parallel bits of stored data;
control means for storing received data in the memory wherein each parallely received bit of data in a set is assigned a memory address having two of the address components the same from bit-to-bit and one of the address components different from bit-to-bit, and for reading data from the memory and supplying it to the output means in the form of successive sets of parallel bits of data wherein each set of parallel bits of data read from the memory has two address components the same from bit-to-bit and one address component different from bit-to-bit, but the address component that is different from bit to bit for the parallel data read from memory is different from the adress component that is different from bit-to-bit in the received data as it was stored in memory.

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Dependencies are inferred from the claim text.