Prefetch buffer and information processing system using the same
OwnerShuuichi Miura, Kenichi Kurosawa +2inventors
InventorsShuuichi Miura, Kenichi Kurosawa, Tetsuaki Nakamikawa, Kenji Hirose
Life of this patent
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OwnerShuuichi Miura, Kenichi Kurosawa +2inventors
InventorsShuuichi Miura, Kenichi Kurosawa, Tetsuaki Nakamikawa, Kenji Hirose
Estimating the term…
A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data searcher for searching, from the data stored in the buffer storage, for data having an address requested by the CPU; and an address estimator for determining an address of data to be prefetched next from the main memory, based on the address requested by the CPU and also on a history of the addresses of data prefetched in the past from the main memory; and an address generator for generating an address of data to be prefetched from the main memory. With this arrangement, it is possible to improve the hit ratio of the prefetch buffer regardless of the direction in which the access address varies.
A data prefetch buffer adapted for use between a cache memory and a main memory in a computer system having a CPU, said data prefetch buffer comprising:
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