Bus interface circuit for controlling data transfer

A bus interface circuit, comprising:

• a first bus having N bits in width, where N is a natural number;
• a second bus;
• transmitting means comprising:
• a transmitting buffer having an upper buffer and a lower buffer;
• first input distributing means, connected to the transmitting buffer, for receiving information from the first bus and inputting the information to the transmitting buffer, and
• first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus;
• receiving means comprising:
• a receiving buffer;
• second input distributing means, connected to the receiving buffer for receiving the information from the second bus and inputting the information to the receiving buffer, and
• second output distributing means, connected to the receiving buffer, for receiving the information from the receiving buffer and outputting the information to the first bus;
• the first input distributing means receiving the information from the first bus and inputting alternately the information to the upper buffer and lower buffer;
• the first output distributing means, having first and second states, wherein each of the first and second states is selected by control signals indicative of the second bus, having a bit width;
• the first state comprising the second bus having N bits in width and the first output distributing means alternately extracting the information from the upper buffer and the lower buffer and alternately transmitting the information to the second bus;
• and
• the second state comprising the second bus having 2N bits in width and the first output distributing means simultaneously extracting the information from the upper buffer and the lower buffer and simultaneously transmitting the information to the second bus.

A bus interface circuit, comprising:

• a first bus having N bits in width, where N is a natural number;
• a second bus;
• transmitting means comprising:
• a transmitting buffer;
• first input distributing means, connected to the transmitting buffer, for receiving information including addresses and data from the first bus and inputting the information to the transmitting buffer, and
• first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus;
• receiving means comprising:
• a receiving buffer having m sub-buffers wherein m is a natural number, each of the m sub-buffers having N bits in width;
• second input distributing means, connected to the receiving buffer, for receiving the information from the second bus and inputting the information to the receiving buffer, and
• second output distributing means, connected to the receiving buffer, for receiving the information from the receiving buffer and outputting the information to the first bus;
• the second input distributing means, having at least first and second states, wherein each of the first and second states is selected by control signals indicative of the second bus having mN bits in width;
• the first state comprising the second bus having mN bits in width, wherein m is equal to 1.0, and the second input distributing means sequentially receiving the information from the second bus and sequentially transmitting the information to m sub-buffers;
• the second state comprising the second bus having mN bits in width, wherein m is not equal to 1.0, and the second input distributing means simultaneously receiving the information from the second bus and simultaneously transmitting the information to m sub-buffers;
• and
• the second output distributing means sequentially extracting the information from the m receiving buffers and sequentially transmitting the information to the first bus.

A bus interface circuit, comprising:

• a first bus having N bits in width, where N is a natural number;
• a second bus;
• transmitting means comprising:
• a transmitting buffer;
• first input distributing means, connected to the transmitting buffer, for receiving information from the first bus and inputting the information to the transmitting buffer, and
• first output distributing means, connected to the transmitting buffer, for receiving the information from the transmitting buffer and outputting the information to the second bus;
• receiving means comprising:
• a receiving buffer having an upper buffer and a lower buffer;
• second input distributing means, connected to the receiving buffer, for receiving the information from the second bus and inputting the information to the receiving buffer, and
• second output distributing means, connected to the receiving buffer (31), for receiving the information from the receiving buffer and outputting the information to the first bus;
• the second input distributing means, having first and second states wherein each of the first and second states is selected by control signals indicative of the second bus, having a bit width;
• the first state comprising the second bus having N bits in width and the second input distributing means alternately receiving the information from the second bus and alternately transmitting the information to the upper buffer and the lower buffer;
• the second state comprising the second bus having 2N bits in width and the second input distributing means simultaneously inputting the information received from the second bus and simultaneously transmitting the information to the upper buffer and the lower buffer;
• and
• the second output distributing means alternately extracting the information from the upper buffer and lower buffer and transmitting the information to the first bus.