Power-up reset override architecture and circuit for flash memory

In a system comprising a microprocessor coupled to a flash memory by a system bus, a method of resetting the flash memory, the reset method comprising the steps of:

• providing a reset signal generation circuit for generating a reset signal when power is applied to the flash memory, the reset signal causing the flash memory to enter a predetermined reset state;
• providing a sleep signal generation circuit coupled to the reset signal generation circuit, the sleep signal generation circuit generating a sleep signal, the sleep signal causing the reset signal generation circuit to enter an energy saving sleep mode when the flash memory is placed in the sleep mode, the reset signal causing the sleep signal generation circuit to reset and suppress generation of the sleep signal;
• and
• providing a reset override signal generation circuit coupled to the reset signal generation circuit, the reset override signal generated during power-up, the reset override signal forcing the reset signal generation circuit to generate the reset signal during power-up even if the reset signal generation circuit is receiving the sleep signal, the reset signal override circuit drawing substantially no power when the flash memory is placed in the sleep mode;
• and
• applying power to the flash memory.

A system comprising:

• a microprocessor;
• a system bus;
• a flash memory coupled to the microprocessor by the system bus, the flash memory having a reset circuit comprising:
• a reset signal generation circuit for generating a reset signal when power is applied to the flash memory, the reset signal causing the flash memory to enter a predetermined reset state;
• a sleep signal generation circuit coupled to the reset signal generation circuit, the sleep signal generation circuit generating a sleep signal, the sleep signal causing the reset signal generation circuit to enter an energy saving sleep mode when the flash memory is placed in the sleep mode, the reset signal causing the sleep signal generation circuit to reset and suppress generation of the sleep signal;
• and
• a reset override signal generation circuit coupled to the reset signal generation circuit, the reset override signal generated during power-up, the reset override signal forcing the reset signal generation circuit to generate the reset signal during power-up even if the reset signal generation circuit is receiving the sleep signal, the reset signal override circuit drawing substantially no power when the flash memory is placed in the sleep mode.

A reset circuit for a flash memory comprising:

• a reset signal generation means for generating a reset signal when power is applied to the flash memory, the reset signal causing the flash memory to enter a predetermined reset state;
• a sleep signal generation means coupled to the reset signal generation means, the sleep signal generation means generating a sleep signal, the sleep signal causing the reset signal generation means to enter an energy saving sleep mode when the flash memory is placed in the sleep mode, the reset signal causing the sleep signal generation means to reset and suppress generation of the sleep signal;
• and
• a reset override signal generation means coupled to the reset signal generation means, the reset override signal generation means for generating a reset override signal, the reset override signal generated during power-up, the reset override signal forcing the reset signal generation means to generate the reset signal during power-up even if the reset signal generation means is receiving the sleep signal, the reset signal override means drawing substantially no power when the flash memory is placed in the sleep mode.