Semiconductor memory device
AssigneeSeiko Epson Corporation
InventorsHirofumi Yasuda, Akira Uematsu
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device for reading data from a selected memory cell. The memory cells are arranged in an array. First bit lines and word lines, coupled to the memory cells, are arranged in a matrix. The word lines select the selected cell. An amplification circuit amplifies the current passing through the selected memory cell and is coupled to the first bit line. A second bit line is coupled to the amplification circuit and carries the amplified current. A sensing circuit coupled to the second bit line senses the current on the second bit line. As a result, the current passing through the selected memory cell is detected.
Claims9
A semiconductor memory device for reading data from a selected memory cell where the memory cells are arranged in an array and first bit lines and word lines coupled to the memory cells are arranged in a matrix, the word lines selecting the selected cell, the semiconductor memory device comprising:
- a first bit line coupled to a group of memory cells for carrying the current passing through the selected memory cell;
- first amplification means coupled to the first bit line for amplifying the current on the first bit line;
- a second bit line coupled to the first bit line through the first amplification means for carrying the amplified current;
- second amplification means coupled to the second bit line for further amplifying the current on the second bit line;
- a third bit line coupled to the second bit line through the second amplification means for carrying the further amplified current;
- and
- sensing means coupled to the third bit line for sensing the current on the third bit line, whereby the current passing through the selected memory cell is detected.
Dependencies are inferred from the claim text.