Memory IC and memory device capable of expansion of storage capacity

A memory device comprising:

• a plurality of memory ICs, each memory IC including:
• a memory element having a chip select signal input terminal;
• a decoder having a plurality of input terminals and output terminals for decoding a portion of an address signal applied to the input terminals to output on a specific output terminal, as a result of the decoding, a chip select signal for enabling the memory element, the specific output terminal being connected to a chip select input terminal of the memory element, and
• a plurality of leads connected to the memory element and to the decoder wherein the particular output terminal of each decoder connected to a respective memory IC differs from memory IC to memory IC.

A memory device comprising:

• at least one integrated circuit including:
• a plurality of input terminals for receiving an address signal,
• a memory element having a plurality of memory locations for storing data in and for supplying stored data from respective memory locations in response to respective enable signals,
• a decoder having an input coupled to some of the plurality of input terminals and a plurality of output terminals coupled to the memory element for decoding a portion of the address signal applied to the input terminals to produce an enable signal applied to the memory element wherein at least one of the address signals applied to the plurality of input terminals produces an enable signal to which the memory element is not responsive;
• and
• selecting means connected to the plurality of output terminals of the decoder for selecting, in response to an external signal, one of the output terminals of the decoder and for connecting the selected output terminal to the memory element to enable the memory element.