Arithmetic-logic unit with modulo addition/substraction function and microprocessor using the same

A data processing apparatus comprising:

• a memory for storing instructions including at least one specific instruction for instructing execution of a predetermined modulo operation;
• an internal bus;
• an arithmetic-logic unit connected to said internal bus;
• a general register connected to said internal bus;
• and
• control means for reading an instruction to be executed from said memory, and, in accordance with said instruction, transferring data from said general register to said internal bus and supplying control signals to said arithmetic-logic unit to begin execution of a predetermined modulo operations,
• wherein said arithmetic-logic unit includes a first operation circuit for executing general operations other than said predetermined modulo operation, a second operation circuit for executing said predetermined modulo operation, and output means for outputting the operation results of said second operation circuit as an output of said arithmetic-logic unit in response to one of said control signals generated by said control means, when said specific instruction is read out from said memory as an instruction to be executed, and
• wherein said second operation circuit includes means for executing an arithmetic-logic operation of judging whether numeric data B cyclically changing within a predetermined range satisfies a predetermined condition with respect to boundary data A and C, each having a modulo value, said data A, B and C being input from said internal bus.

An arithmetic-logic unit for executing a predetermined operation of given data, said operation being specified by a microinstruction, comprising:

• three data input ports for inputting data A, B and C;
• input latches responsive to input enable signals for latching said input data A, B and C at said data input ports;
• a first operation circuit for executing an arithmetic-logic operation of (A.+-.B) mod (C+1) for said input data A, B and C;
• a second operation circuit for determining whether said input data A, B and C satisfy at least one of the relationships of A.ltoreq.B.ltoreq.C, A.ltoreq.B<C, A<B.ltoreq.C and A<B<C from a modulo operation viewpoint;
• a third operation circuit for executing an arithmetic-logic operation of two of said data A, B, and C input from two of said input ports;
• and
• means for selectively outputting one of the operation results of said operation first, second and third circuits in accordance with said microinstruction.

A communication controller comprising:

• first interface means for communicating with a host system;
• second interface means for communicating with a network;
• buffer memory means connected between said first and second interface means for temporarily storing data to be transmitted to said one of said host system and said network;
• and
• processor means coupled with said buffer memory means and said first and second interface means;
• wherein said processor means comprises:
• first modulo operation means responsive to a modulo comparison instruction for executing an arithmetic-logic operation of determining whether numeric data B satisfies a predetermined condition with respect to boundary data A and C, each having a modulo value;
• second modulo operation means responsive to modulo addition/subtraction instructions, for executing an arithmetic-logic operation of (A.+-.B) mod (C+1) for designated data A, B and C;
• and
• third operation means responsive to instructions other than said modulo comparison and modulo addition/subtraction instructions, for executing arithmetic-logic operations other than that executed by said first and second modulo operation means.