Logic circuit simulator for verifying circuit operations having MOS transistors

A logic simulator for verifying a circuit operation of a logic circuit including MOS transistors, said logic simulator comprising:

• circuit connection data providing means for providing a circuit connection data specifying circuit connections in said logic circuit;
• input pattern signal providing means for applying an input pattern signal to an input portion of said logic circuit;
• event generating means for generating a signal value change (an event) at input and output portions of elements of said logic circuit in said circuit connection data as a function of said input pattern signal to output a circuit connection data with event generation;
• MOS transistor input signal extracting means for extracting an MOS transistor having input and control terminals at which the event is generated as a function of said circuit connection data with event generation to output said MOS transistor as an event generation MOS transistor (an event generation MOST);
• and
• MOS transistor output signal level determining means for detecting said event generation MOST which is turned on as a function of a conductivity type of said event generation MOST and a control signal value given from said control terminal to determine an output signal level given from an output terminal when said event generation MOST is turned on as a function of an input signal value, said MOS transistor output signal level determining means verifying the presence of the danger that a through current is generated in said event generation MOST as a function of said conductivity type and a signal level of said control signal value of said event generation MOST.

A logic simulator for verifying a circuit operation of a logic circuit including MOS transistors, said logic simulator comprising:

• circuit connection data providing means for providing a circuit connection data specifying circuit connections in said logic circuit;
• input pattern signal providing means for applying an input pattern signal to an input portion of said logic circuit;
• event generating means for generating a signal value change (an event) at input and output portions of elements of said logic circuit in said circuit connection data as a function of said input pattern signal to output a circuit connection data with event generation;
• MOS transistor input signal extracting means for extracting an MOS transistor having input and control terminals at which the event is generated as a function of said circuit connection data with event generation to output said MOS transistor as an event generation MOS transistor (an event generation MOST);
• MOS transistor output signal delay time determining means for detecting said event generation MOST which is turned on as a function of a conductivity type of said event generation MOST and a control signal value given from said control terminal to determine a state transition delay time of an output signal given from an output terminal from an input signal when said event generation MOST is turned on as a function of an input signal value;
• and
• simulation time control means for controlling a signal generation timing of said output signal of said event generation MOST as a function of said state transition delay time.

A logic simulator for constructing a circuit connection data in the form of a logic circuit model equivalent to a logic circuit and performing a logic simulation as a function of an input signal trigger to be applied from the exterior of said logic circuit to verify the design of said logic circuit, said logic simulator comprising:

• circuit constant data providing means for applying a transistor circuit constant data to elements constituting said circuit connection data;
• element selecting means for selecting a specified element group causing a signal value competition in said circuit connection data as elements to which a signal strength data is to be set;
• data extracting means for extracting said transistor circuit constant data applied to said specified elements as a reference circuit constant;
• .beta. calculating means for calculating transistor gain coefficients .beta. as a function of said reference circuit constant and process parameters for fabrication of said logic circuit;
• classifying means for determining signal strength data for respective elements of said specified element group as a function of the magnitude of said gain coefficients .beta.;
• signal strength data providing means for setting said signal strength data to a circuit connection data for logic simulation;
• and
• logic simulation executing means at a plural signal strength level for applying an input signal to said circuit connection data for logic simulation to execute the logic simulation.