Digital .SIGMA.-.DELTA. modulator
AssigneeKabushiki Kaisha Toshiba
InventorsMitsuru Nagata, Koichiro Sato, Tsunetaka Matsuo
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AssigneeKabushiki Kaisha Toshiba
InventorsMitsuru Nagata, Koichiro Sato, Tsunetaka Matsuo
Estimating the term…
A counter counts a clock signal. A multiplexer sequentially inputs digital input signals each having a plurality of bits in accordance with an output signal from the counter. A subtracter subtracts a quantized output signal delayed by an n-clock delay element from the input signal. An integrator integrates an output signal from the subtracter. The quantizer quantizes an output from the integrator. The n-clock delay element delays the output signal from the quantizer by n clocks and supplies the delayed signal to the subtracter. A demultiplexer sequentially outputs output signals from the quantizer in accordance with the output signal from the counter. This demultiplexer outputs signals in the input order of the multiplexer.
A digital .SIGMA.-.DELTA. modulator comprising:
A digital .SIGMA.-.DELTA. modulator comprising:
A digital .SIGMA.-.DELTA. modulator comprising:
A digital .SIGMA.-.DELTA. modulator comprising:
Dependencies are inferred from the claim text.