Low power V.sub.cc and temperature independent oscillator

The low power oscillator circuit for refreshing a DRAM comprising:

• a constant current source which is substantially independent of variations in a supply voltage Vcc and temperature, wherein the constant current source includes first and second p-channel transistors coupled between a first voltage connection and a second voltage connection;
• wherein the gate electrode of the first transistor is coupled to the source of the second transistor and the gate electrode of the second transistor is coupled to the drain of the first transistor;
• first and second resistors, wherein said first resistor is coupled between the drain of the first transistor and the first voltage connection and the second resistor is coupled between the source of the second transistor and the second voltage connection;
• and
• wherein the source of the first transistor is coupled to the second voltage connection and the drain of the second transistor outputs a constant current;
• a capacitor coupled to the constant current source to substantially establish the period of oscillation determined by the current generated in the constant current source;
• said constant current source and said capacitor forming a first delay circuit;
• a current limiting circuit coupled to said capacitor to limit current loss and power dissipation;
• a latch coupled to said current limiting circuit to provide a stable output;
• a second delay circuit including a series of inverters coupled to receive the output from said latch and provide an oscillating output pulse signal which is inversely proportional to V.sub.CC ;
• and
• an electrical connection from the second delay circuit to said first delay circuit.

A low power oscillator circuit comprising:

• a first delay circuit including a constant current source which is substantially independent of variations in a supply voltage Vcc and temperature and a charge storage device coupled to the constant current source to establish a period of oscillation determined by a current generated in the constant current source;
• a differential amplifier coupled to the charge storage device to provide an output when the charge storage device is charged to a certain voltage by the constant current source;
• a latch coupled to the output of the differential amplifier to provide a stable output;
• a second delay circuit coupled to receive the output from said latch and provide an oscillating output pulse signal;
• and
• an electrical connection from the second delay circuit to said first delay circuit.

An integrated circuit low power oscillator circuit for use in refreshing a DRAM comprising:

• a constant current source which is substantially independent of variations in a supply voltage Vcc and temperature, wherein the constant current source includes first and second p-channel transistors coupled between a first voltage connection and a second voltage connection;
• wherein the gate electrode of the first transistor is coupled to the source of the second transistor and the gate electrode of the second transistor is coupled to the drain of the first transistor;
• first and second resistors, wherein said first resistor is coupled between the drain of the first transistor and the first voltage connection and the second resistor is coupled between the source of the second transistor and the second voltage connection;
• and
• wherein the source of the first transistor is coupled to the second voltage connection and the drain of the second transistor outputs a constant current;
• a capacitor coupled to the constant current source to substantially establish the period of oscillation determined by the current generated by the constant current source;
• said constant current source and said capacitor forming a first delay circuit;
• a differential amplifier coupled to the capacitor to provide an output when the capacitor is charged to a certain voltage by the constant current source, said differential amplifier having transistors with long channel lengths to limit current loss from V.sub.CC to ground;
• a current limiting circuit coupled to said differential amplifier to limit current loss and power dissipation;
• a latch coupled to said current limiting circuit to provide a stable output;
• a second delay circuit including a series of inverters coupled to receive the output from said latch and provide an oscillating output pulse signal;
• and
• an electrical connection from the second delay circuit to said first delay circuit.

A method of generating an oscillating output that consumes low power comprising the steps of:

• providing a substantially constant current using a low power current source;
• generating a controlled first delay based upon the constant current;
• generating a second delay based on a series of cascaded inversions;
• using an electrical signal that is generated subsequent to said first delay for generating further iterations of said controlled first delay;
• and
• outputting an oscillating signal, wherein a period of oscillation of said oscillating signal is substantially determined by said first delay.

A low power method of generating an oscillating signal for an integrated circuit comprising the steps of:

• using a first delay circuit for generating first pulses, including controlling the power consumption not to exceed about 11 microamperes;
• and
• using a second delay circuit to generate second pulses on said first pulses;
• wherein the first pulse has a period that is at lest one order of magnitude greater than a period of the second pulse.