Differential amplification circuit
AssigneesFujitsu Limited, Fukitsu VLSI Limited
InventorEisaku Itoh
Life of this patent
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Abstract
The sources of first and second N-channel MOS transistors are interconnected. A complementary input signal is inputted to the gates of the first and second N-channel MOS transistors, and a complementary output signal is outputted from their drains. Switch circuits are respectively connected between the source of the first or the second N-channel MOS transistors, and the interconnected sources of the first and second N-channel MOS transistors. Each switch circuit differs from the N-channel MOS transistor to which the switch circuit is connected. The opening and closing operations of the switch circuit are controlled, based on a complementary signal from the respective MOS transistor.
Claims12
A differential amplification circuit comprising:
- a first N-channel MOS transistors having a source terminal, a drain terminal for outputting a first output signal, and a gate for receiving a first input signal;
- a second N-channel MOS transistor having a source terminal, a drain terminal for outputting a second output signal complementary to said first output signal, and a gate terminal for receiving a second input signal complementary to said first input signal;
- first switch means for connecting said source terminal of said first N-channel MOS transistor to a common potential point, in response to said second output signal;
- and
- second switch means for connecting said source terminal of said second N-channel MOS transistor to said common potential point, in response to said first output signal.
A differential amplification circuit comprising:
- a first P-channel MOS transistor having a source terminal, a drain terminal for outputting a first output signal, and a gate terminal for receiving only a first input signal;
- a second P-channel MOS transistor having a source terminal, a drain terminal for outputting a second output signal complementary to said first output signal, and a gate terminal for receiving only a second input signal;
- first switch means for connecting said drain terminal of said first P-channel MOS transistor to a common potential point, in response to said second output signal;
- and
- said second switch means for connecting said drain terminal of said second P-channel MOS transistor to said common potential point, in response to said first output signal.
Dependencies are inferred from the claim text.