Precision MOS resistor
AssigneeSilicon Systems, Inc.
InventorsBert White, Mehrdad Negahban-Hagh
Life of this patent
Estimating the term…
Abstract
A precision resistor using MOS devices. The present invention utilizes an NMOS resistive element to simulate the resistor. A pair of PMOS source followers are implemented to control the value of the resistor and cancel the non-linearity due to the drain-source voltage V.sub.ds. A pair of NMOS source followers serve to eliminate non-linear distortions due to the "body effect" that can exist in the resistive element. The resistor circuit of the present invention provides higher precision, linearity and high value resistors in a smaller area than prior art MOS resistors.
Claims47
A circuit comprising:
- a resistive element having a first terminal and a second terminal, said resistive element further having a first impedance terminal and a second impedance terminal between which an impedance exists, said resistive element comprising a first and second transistor of a first conductivity type, and wherein a source of said first transistor is coupled to a source of said second transistor and a drain of said first transistor is coupled to a drain of said second transistor;
- a first biasing means coupled to said first terminal of said resistive element;
- a second biasing means coupled to said second terminal of said resistive element;
- said first and second biasing means for linearly controlling said impedance of said resistive element.
A circuit comprising:
- a resistive element;
- a first biasing means coupled to a first terminal of said resistive element;
- a second biasing means coupled to a second terminal of said resistive element;
- said resistive element having a first impedance terminal and a second impedance terminal between which an impedance exists, said resistive element comprising a first and second transistor of a first conductivity type, wherein a source of said first transistor is coupled to a source of said second transistor and a drain of said first transistor is coupled to a drain of said second transistor;
- said first and second biasing means for linearly controlling said impedance of said resistive element;
- a third biasing means coupled to a third terminal of said resistive element for improving a linearity of said resistive element;
- a fourth biasing means coupled to a fourth terminal of said resistive element for improving said linearity of said resistive element.
A circuit comprising:
- a first and second resistive elements, said first resistive element further having a first impedance terminal and a second impedance terminal between which a first impedance exists, said second resistive element further having a third impedance terminal and a fourth impedance terminal between which a second impedance exists, said first resistive element comprising a first and second transistor of a first conductivity type, wherein a source of said first transistor is coupled to a source of said second transistor and a drain of said first transistor is coupled to a drain of said second transistor, said second resistive element comprising a third and fourth transistor of said first conductivity type, wherein a source of said third transistor is coupled to a source of said fourth transistor and a drain of said third transistor is coupled to a drain of said fourth transistor;
- a first biasing means coupled to a first terminal of said first resistive element;
- a second biasing means coupled to a second terminal of said first resistive element and coupled to a first terminal of said second resistive element;
- a third biasing means coupled to a second terminal of said second resistive element;
- said first, second and third biasing means for linearly controlling the impedance of said first and second resistive elements.
The circuit of claim 46 wherein said second conductivity type is P-type.
Dependencies are inferred from the claim text.