Synchronous separating circuit

A synchronous separating circuit comprising:

• a comparator having an inverting input maintained at a bias voltage, a non-inverting input, and an output;
• a capacitor having a first electrode connected to said non-inverting input and a synchronous signal input into a second electrode;
• a first circuit providing a substantially constant current to said non-inverting input when said output of the comparator is at a low level;
• a second circuit including a constant current source for discharging from said non-inverting input at a substantially constant rate at least when said output of said comparator is in a high level, wherein the second circuit includes a constant "voltage source".

A synchronous separating circuit comprising:

• a comparator having an inverting input maintained at a bias voltage, a non-inverting input, and an output;
• a capacitor having a first electrode connected to said non-inverting input and a synchronous signal input into a second electrode;
• a first circuit providing a substantially constant current to said non-inverting input when said output of the comparator is at a low level;
• a second circuit including a constant current source for discharging from said non-inverting input at a substantially constant rate at least when said output of said comparator is in a high level, wherein the second circuit includes a current "mirror circuit."

A synchronous separating circuit comprising:

• a comparator having a first input node supplied with a bias voltage, a second input node, and an output node;
• a signal input terminal receiving a composite video signal;
• a capacitor connected between said signal input terminal and said second input node of said comparator;
• a first transistor connected between a first voltage line and said second input node of said comparator and controlled by an output signal at said output node of said comparator such that said first transistor is rendered conductive to charge said capacitor when said output signal takes a first logic level and non-conductive to stop charging said capacitor when said output signal takes a second logic level;
• a second transistor connected between a second voltage line and said second input node of said comparator;
• and
• a bias circuit coupled to said second transistor to bias said second transistor such that said second transistor flows a substantially constant current therethrough irrespective of said output signal at said output node of said comparator.