Integrated circuit with programmable speed/power adjustment

A programmable logic device having an array of logic devices and a plurality of sense amplifiers with adjustable speed-power characteristics, comprising:

• a programmable logic device having a plurality of sense amplifiers, each included in a current path which draws a predetermined amount of current;
• a plurality of impedance elements connectable to said integrated circuit in a manner to control current flow in said current path;
• a plurality of electrically erasable programmable read-only memories each coupled to one of said plurality of impedance elements, whereby each of the impedance elements can be connected or disconnected by setting its electrically erasable programmable read-only memory, thereby adjusting the operating speed and the power consumption of the programmable logic device by varying the total impedance of the plurality of impedance elements so as to adjust the current through the sense amplifiers according to the speed/power requirements of the integrated circuit.