US 5,345,110 A · Low-power fuse detect and latch circuit

Abstract

This invention is a low-power circuit for detecting and latching the state of a fusible link. During a power-up sequence, the circuit makes a one time determination regarding the blown or unblown status of a fuse element. In one embodiment of the invention, the circuit comprises a fuse detect node which is coupled to power supply voltage (V.sub.cc) through a first IGFET and to ground through a second IGFET (which, in this embodiment, has more drive than the first) and the fuse element, respectively, when the fuse element is not severed. In another embodiment of the invention, the fuse detect node is coupled to ground through the second IGFET, and to power supply voltage (V.sub.cc) through the first IGFET (which, in this embodiment, has more drive than the second) and the fuse element, respectively, when the fuse element is not severed. During a first portion of the power-up sequence, both first and second IGFETs are rendered conductive, thus allowing the fuse detect node to reach equilibrium with respect to charge. The equilibrium charge state will depend on whether or not the fuse is severed or intact, and this charge state is reflected in a latched output. Once the output has been latched, whether in a low or high state, the first and second MOSFETs are rendered nonconductive during a second portion of the power-up sequence, thus isolating the fuse detect node from V.sub.cc and ground. The output is used to select or deselect a feature option or redundant circuit element.

Claims20

Dependent claims

A low-power circuit for detecting and latching the state of a fusible link, said circuit comprising:

an input node;
an output node;
a fuse element which, at the time of circuit manufacture, provides a closed connection, but which can be selectively severed to provide an open connection;
first and second transistors responsive to a digital input signal on said input node, said second transistor having a greater drive value than said first transistor;
a fuse detect node which is coupled to said output node via a latch circuit, to power supply voltage through said first transistor, and to ground through said second transistor and said fuse element, respectively, when said fuse element is in an unsevered state.

2 more elements

A low-power circuit for detecting and latching the state of a fusible link, said circuit comprising:

an input node;
an output node;
a fuse detect node which is coupled to said output node via a latch circuit;
a fuse element which, at the time of circuit manufacture, provides a closed connection, but which can be selectively severed with a pulse of coherent electromagnetic energy to provide an open connection;
first and second transistors responsive to a digital input signal on said input node;
said first transistor coupling said fuse detect node to a power supply rail, and said second transistor coupling said fuse detect node to a ground rail, when said fuse element is unsevered;
said first transistor, thereby being associated with said power supply rail;
and said second transistor thereby being associated with said ground rail;
said fuse element being interposed between one of said rails and the transistor associated with that one rail;
said first transistor having a greater drive value than said second transistor when said fuse element is interposed between the power supply rail and said first transistor, but having a smaller drive value than said second transistor when said fuse element is interposed between the ground rail and said second transistor.

7 more elements

Dependencies are inferred from the claim text.

Low-power fuse detect and latch circuit

Life of this patent

Low-power fuse detect and latch circuit

Life of this patent

Abstract

Claims20