US 5,345,109 A · Programmable clock circuit

Abstract

The programmable clock circuit of the present invention provides the means to generate lower frequency clock signals from a higher clock frequency signal while maintaining the synchronous relationship of the signals as well as compatible electrical characteristics of the signal. The advantages to the circuit are realized in a system in which the processor core operates at a first higher frequent clock frequency while components coupled to the processor, such as memory, operate at a lower frequency. In order to maintain electrical and timing compatibility, it is desirable to derive the lower clock frequency used to communicate with external components from the clock frequency utilized by the processor core. In the clock circuit of the present invention, the high frequency input clock signal is input to the clock circuit which has the ability to generate multiple lower frequency output signals. The actual signal output is programmable to conform to system clock requirements. Clock signals at the programmed lower frequency are then generated from the selected output signal.

Claims47

Dependent claims

A programmable circuit for generating lower frequency clock signals from a higher first frequency clock signal, said circuit comprising:

a first logic gate having a data input and clock input, the gate generating an output corresponding to the input on a first edge of the clock input signal, said first frequency clock signal input to the clock input of the first logic gate;
a first inverter coupled to receive as input an output of the first logic gate and generating a first inverted output;
a second inverter which receives as data input the first inverted output of the first inverter and generates a second inverted output;
a second logic gate having a data input and ock input, the gate generating an output corresponding to the input on a first edge of the clock input signal, said second logic gate receiving as data input the second inverted output of the second inverter, said first frequency clock signal input to the clock input;
a third inverter coupled to receive the output of the second logic gate and generates a third inverted output;
a logical AND gate to logically AND the first inverted output of the first inverter and the third inverted output of the third inverter;
a first switch coupled to receive the first inverted output of the first inverter, said first switch, when in an enabled state, generating as output a second frequency clock signal slower than the first frequency clock signal;
a second switch coupled to receive the output of the logical AND gate, said second switch, when in an enabled state, generating as output a third frequency clock signal slower than the first frequency clock signal.

5 more elements

A programmable circuit for generating lower clock frequencies from a higher first clock frequency, said circuit comprising:

a first gate means having a data input and clock input, the gate means generating an output corresponding to the input on an edge of a clock input signal, said first frequency clock signal input to the clock input of the first gate means;
a first inverter means coupled to receive as input an output of the first gate means and generating a first inverted output;
a second inverter means coupled to receive as data input the first inverted output of the first inverter means and generates a second inverted output;
a second gate means having a data input and clock input, the gate means generating an output corresponding to the input on an edge of the clock input, said second gate means receiving as data input the second inverted output of the second inverter means, said first clock frequency input to the clock input;
a third inverter means coupled to receive the output of the second gate means and generates a third inverted output;
ANDing means to logically AND the first inverted output of the first inverter and the third inverted output of the third inverter means;
a first switch means coupled to receive the first inverted output of the first inverter means, said first switch, when in an enabled state, generating as output a second frequency clock signal slower than the first frequency clock signal;
a second switch means coupled to receive the output of the ANDing means, said second switch, when in an enabled state, generating as output a third frequency clock signal slower than the first frequency clock signal.

5 more elements

A processing system comprising:

a processor driven by a processor clock signal operating at a processor clock frequency;
at least one component coupled to the processor;
an input clock means for providing an input clock signal to the processing system;
a processor clock means for generating the processor clock signal from the input clock signal;
a clock circuit coupled to the processor clock means for generating lower frequency clock signals from the processor clock signal, said lower frequency clock signals utilized by the processor to communicate with the component, which operates at a clock frequency lower than the frequency of the processor clock signal, said clock circuit comprising;
a first gate means having a clock input coupled to receive the processor clock signal and a data input, the gate means generating an output corresponding to the input on an edge of the processor clock signal,
a first inverter means coupled to receive as input an output of the first gate means and generating a first inverted output;
a second inverter means which receives as data input the first inverted output of the first inverter means and generates a second inverted output;
a second gate means having a clock input coupled to receive the processor clock signal and a data input, the second gate means generating an output corresponding to the input on an edge of the processor clock signal, said second gate means receiving as data input the second inverted output of the second inverter means, said first frequency clock signal input to the clock input;
a third inverter means coupled to receive the output of the second gate means and generates a third inverted output;
ANDing means to logically AND the first inverted output of the first inverter and the third inverted output of the third inverter means;
a first switch means coupled to receive the first inverted output of the first inverter means, said first switch, when in an enabled state, generating as output a second frequency clock signal slower than the first frequency clock signal;
a second switch means coupled to receive the output of the ANDing means, said second switch, when in an enabled state, generating as output a third frequency clock signal slower than the first frequency clock signal.

10 more elements

Dependencies are inferred from the claim text.

Programmable clock circuit

Life of this patent

Programmable clock circuit

Life of this patent

Abstract

Claims47