Verifying dynamic memory refresh

A method for verifying refreshing of a cell of a system capable of self refreshing, the method comprising the steps of:

• storing data in the cell;
• enabling self refreshing;
• directing self refreshing at a first time by inputting to the system a test signal so that refreshing of the cell begins on receipt of the test signal;
• disabling self refreshing at a second time;
• reading data from the cell;
• determining that the period from the first time to the second time is sufficient for refreshing by comparing the data read to the data stored.

A method for verifying refreshing of a cell of a system capable of self refreshing, the method comprising the steps of:

• storing data in the cell;
• enabling self refreshing;
• enabling the output of a refresh cycle signal occurring at a first time;
• disabling self refreshing at a second time;
• reading data from the cell;
• and
• determining that the period from the first time to the second time is sufficient for refreshing by comparing the data read to the data stored.

A system for providing an output data signal, the system responsive to a first control signal, a second control signal, an input data signal, and a test signal, the system comprising:

• a. a dynamic storage cell;
• b. means, coupled to the cell, for storing data in the cell in response to the input data signal and the first control signal, and for providing the output data signal in response to the second control signal;
• c. refreshing means, coupled to the cell, for refreshing the cell after an absence of the first and the second control signal for a first time, the refreshing means providing a refresh cycle signal;
• and
• d. detecting means, coupled to the refreshing means, for enabling outputting of the refresh cycle signal in response to the test signal.

A dynamic memory, responsive to an address signal, and an address strobe having a transition, the memory providing a data signal, the memory comprising:

• a. a first line for conveying a portion of the address signal and for conveying a first signal;
• b. a latch coupled to the first line and responsive to the address signal and to the address strobe for providing a latched address signal;
• c. a counter for providing a refresh address signal after receiving a second selected signal;
• d. a timer for measuring a predetermined time, for providing a first control signal after an absence of the address strobe for the predetermined time, and for providing a first start signal;
• e. a second line for conveying a second signal;
• f. a detector coupled to the first line for providing a second control signal when the first signal is received;
• g. a first switch, coupled to the timer and enabled responsive to the first control signal, the first switch for providing a first selected signal, the first selected signal responsive to the refresh address signal when enabled, the first selected signal responsive to the latched address signal when disabled;
• h. a second switch, coupled to the detector and enabled responsive to the second control signal, the second switch for providing the second selected signal, the second selected signal responsive to the second start signal when enabled, the second selected signal responsive to the first start signal when disabled;
• i. a dynamic memory cell for providing the data signal responsive to stored data, the cell coupled to the first switch and responsive to the first selected signal so that when the first switch is enabled the memory cell begins refreshing after the occurrence of the second selected signal;
• j. wherein refreshing is interrupted when the address strobe transition is received during refreshing;
• and
• k. wherein the data signal conveys stored data when refreshing was completed without interruption.

A dynamic memory, responsive to an address signal, and an address strobe having a transition, the memory providing a data signal, the memory comprising:

• a. a first line for conveying a portion of the address signal and for conveying a first signal;
• b. a latch coupled to the first line and responsive to the address signal and to the address strobe for providing a latched address signal;
• c. a counter for providing a refresh address signal after receiving a start signal;
• d. a timer for measuring a predetermined time, for providing a first control signal after an absence of the address strobe for the predetermined time, and for providing the start signal;
• e. a detector coupled to the first line for providing a second control signal when the first signal is received;
• f. a first switch, coupled to the timer and enabled responsive to the first control signal, the first switch for providing a first selected signal, the first selected signal responsive to the refresh address signal when enabled, the first selected signal responsive to the latched address signal when disabled;
• g. a dynamic memory cell for providing the data signal responsive to stored data, the cell coupled to the first switch and responsive to the first selected signal so that when the first switch is enabled the memory cell begins refreshing after the occurrence of the start signal;
• h. a second line for conveying the data signal and a buffered signal;
• i. a buffer for providing on the second line, when enabled by the second control signal, the buffered signal in response to the start signal;
• j. wherein refreshing is interrupted when the address strobe transition is received during refreshing;
• and
• k. wherein the data signal conveys stored data when refreshing was completed without interruption.