Semiconductor memory device

A semiconductor memory device of a stacked structure having a plurality of memory cells, each of said memory cells comprising:

• a transistor formed on a surface of a semiconductor substrate having first, second and third terminals;
• and
• a capacitor formed on said semiconductor substrate having lower and plate electrodes, said lower electrode including,
• a principal portion formed in a generally column configuration,
• a peripheral portion spaced from and surrounding an outer side surface of a wall of said principal portion with the height of said principal portion being generally the same as the height of said peripheral portion which surrounds said principal portion, and
• a bottom portion integrating an end of said principal portion and an end of said peripheral portion and connected to said first terminal of said transistor;
• said plate electrode formed on a capacitor insulating layer disposed over respective portions of said principal portion, said peripheral portion and said bottom portion of said lower electrode and said plate electrode extends over both an inner side surface and an outer side surface of a wall of said peripheral portion of said lower electrode so that both said inner side surface and said outer side surface of a wall of said peripheral portion define capacitive surface area of said lower electrode.

A semiconductor memory device of a stacked structure having a plurality of memory cells, each of said memory cells comprising:

• a transistor formed on a surface of a semiconductor substrate having first, second and third terminals;
• and
• a capacitor formed on said semiconductor substrate having lower and plate electrodes, said lower electrode including,
• a principal portion formed in a generally cup-shaped configuration,
• a peripheral portion spaced from and surrounding an outer side surface of a wall of said principal portion with the height of said principal portion being generally the same as the height of said peripheral portion which surrounds said principal portion, and
• a bottom portion integrating an end of said principal portion and an end of said peripheral portion and connected to said first terminal of said transistor;
• said plate electrode formed on a capacitor insulating layer disposed over respective portions of said principal portion, said peripheral portion and said bottom portion of said lower electrode and said plate electrode extends over both an inner side surface and an outer side surface of a wall of the peripheral portion of said lower electrode so that both said inner side surface and said outer side surface of a wall of the peripheral portion define capacitive surface area of said lower electrode.

A semiconductor memory device of a stacked structure having a plurality of memory cells, each of said memory cells comprising:

• a transistor formed on a surface of a semiconductor substrate having first, second and third terminals;
• and
• a capacitor formed on said semiconductor substrate having lower and plate electrodes, said lower electrode including,
• a principal portion formed in a generally column configuration,
• a peripheral portion spaced from and surrounding an outer side surface of a wall of said principal portion, and
• a bottom portion integrating an end of said principal portion and an end of said peripheral portion and connected to said first terminal of said transistor;
• said plate electrode formed on a capacitor insulating layer disposed over respective portions of said principal portion, said peripheral portion and said bottom portion of said lower electrode and said plate electrode extend over both an inner side surface and an outer side surface of a wall of said peripheral portion of said lower electrode so that both said inner side surface and said outer side surface of a wall of said peripheral portion define capacitive surface area of said lower electrode and said lower electrode of said capacitor further comprises a plurality of peripheral portions and bottom portions.

A semiconductor memory device having a plurality of memory cells, each of said memory cells comprising:

• a transistor formed on a surface of a semiconductor substrate and having a first terminal;
• and
• a capacitor formed on the semiconductor substrate and having first and second electrodes, said first electrode being connected with said first terminal of the transistor;
• said first electrode of the capacitor including,
• a principal portion of a generally cup-shaped configuration,
• a peripheral portion spaced from and surrounding an outer side surface of a wall of the principal portion with the height of said principal portion being generally the same as the height of said peripheral portion which surrounds said principal portion, and
• a bottom portion connecting an end of the principal portion with an end of the peripheral portion;
• and
• said second electrode of the capacitor including respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode and said second electrode extending over an inner side surface and an outer side surface of a wall of the peripheral portion of the first electrode so that both said inner side surface and said outer side surface of the wall of the peripheral portion define capacitive surface area of said first electrode.