Semiconductor memory device having a meshlike grounding wiring
AssigneeNEC Corporation
InventorsMasayoshi Ohkawa, Fumihiko Hayashi
Life of this patent
Estimating the term…
Loading patent…
AssigneeNEC Corporation
InventorsMasayoshi Ohkawa, Fumihiko Hayashi
Estimating the term…
In an SRAM having TFT type memory cells, a pair of driver transistors and a pair of access transistors formed of N-channel MOS transistors on a silicon substrate are respectively arranged at positions point symmetric with respect to the center of gravity of the memory cell, and a pair of load transistors formed of P-channel type TFTs is also arranged in point symmetric positions with respect to the center of gravity. The gate electrodes of these N-channel MOS transistors and a word line are formed of a first layer of conductor film, a grounding wiring within the memory cell is formed of a second layer of conductor film, and TFTs are formed of a third and a fourth layers of conductor films. Two connecting holes for the digit lines and the drain regions of the access transistors are also arranged distributed point symmetric with respect to the center of gravity. As a result, the grounding wiring is extended respectively in the direction parallel to the word line and in the direction parallel to the digit lines, forming a meshlike shape. The relative resistance value of the grounding wiring is decreased and its bit dependence is also reduced. Because of this, the detection sensitivity at the time of read is improved. Moreover, due to the above-mentioned shape of the grounding wiring, the space between the channel region of the TFT and the gate electrode of the driver transistor can be shielded by the grounding wiring, and the leakage characteristic of the TFT can be improved.
In a semiconductor memory device in which one static memory cell includes first and second load transistors consisting of P-channel type thin film transistors, a first and second driver transistors including an N-channel MOS transistor formed on the surface of a silicon substrate, first and second access transistors including an N-channel MOS transistor formed on the surface of said silicon substrate, a word line, first and second digit lines, a power supply wiring, and a first grounding wiring, the gate electrodes of said first and said second driver transistors and the gate electrodes of said first and said second access transistors that also serve as said word lines are formed of a first conductor film consisting of a material having a melting point higher than that of aluminum, said first grounding wiring within said memory cell being formed of a second conductor film including a material having a melting point higher than that of aluminum, wherein said first grounding wiring is connected to a second grounding wiring formed of an aluminum film in a predetermined region outside of said memory cell, and said first and said second load transistors being formed of a third conductor film including a material having a melting point higher than that of aluminum and a fourth conductor film consisting of a material having a melting point higher than that of aluminum:
Dependencies are inferred from the claim text.