Semiconductor memory cell

A memory cell for a semiconductor device comprising:

• a semiconductor substrate having first and second active device regions;
• a first CMOS inverter overlying the first active region;
• a second CMOS inverter overlying the second active region;
• first and second word lines spaced apart by the first and second CMOS inverters and overlying a portion of the first and second active regions;
• a first Vss region in a portion of the first active region passing under a first portion of the first word line and electrically coupled to the first CMOS inverter;
• and
• a second Vss region in a portion of the second active device region passing under a first portion of the second word line and electrically coupled to the second CMOS inverter.

A memory cell for a semiconductor device comprising:

• a semiconductor substrate having a principal surface;
• first and second active regions in the substrate, each active region having first and second elongated opposed parallel sides and first and second narrow opposed parallel sides;
• first and second CMOS inverters overlying a central portion of the first and second active regions respectively,
• each CMOS inverter having a shared-gate electrode disposed in a direction parallel to the narrow sides of the first and second active regions, and
• each CMOS inverter having elevated source and drain regions overlying the principal surface in the first and second active regions and spaced apart by the shared gate electrode, and
• each CMOS inverter having thin-film source and drain regions overlying the shared gate electrode and the elevated source and drain regions and spaced apart therefrom by an insulating layer;
• first and second word lines overlying the first and second active regions disposed in a direction parallel to the shared-gate electrodes and separated by the first and second CMOS inverters;
• first and second Vss connection means electrically coupling a Vss signal from a Vss signal line external to the memory cell to the elevated source regions of the first and second CMOS inverters respectively;
• and
• first and second Vdd connection means electrically coupling a Vdd signal to the first and second CMOS inverters.

A memory cell for a semiconductor device comprising:

• a substrate having a principal surface;
• an active region formed in the substrate;
• first elevated source and drain regions of a first conductivity type in the active region overlying the principal surface and spaced apart by a shared gate electrode;
• thin-film source and drain regions of a second conductivity type overlying the shared gate electrode and the elevated source and drain regions and separated therefrom by an insulating layer;
• a gate extension overlying at least a portion of the active region and spaced apart from the shared gate electrode by the elevated drain region;
• a pass gate electrode overlying the active region and spaced apart from the gate extension by a second elevated drain region of the first conductivity type;
• an electrically isolated word line overlying the active region and spaced apart from the shared gate electrode by the first elevated source region;
• a Vss contact region overlying the active region and spaced apart from the first elevated source region by the isolated word line;
• a doped region in the active region underlying the isolated word line electrically coupling the Vss contact region to the first elevated source region;
• and
• a shared contact wherein a metallurgical junction is formed between the first and second elevated drain regions, the gate extension, and the thin-film drain region.