US 5,333,291 A · Stride enhancer for high speed memory accesses with line fetching mode and normal mode employing boundary crossing determination

Abstract

A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride independent. In the preferred implementation, the BSM has two fetch modes; a normal mode and a line fetch mode. In the normal mode, a quadword (QW) is fetched as in the conventional design. In the line fetch mode, all double words (DWs) within the referenced line are returned to the storage control element (SCE) at two DWs per cycle for strides one through eight (twice the conventional bandwidth) or at least one DW per cycle for all other strides (equal to the conventional bandwidth). This is accomplished with two DW busses rather than a single QW bus and by interleaving DW storage locations within the BSM. In line fetch mode for strides one through eight, DWs are read out according to the stride on the two DW busses.

Claims9

Dependent claims

A memory system for a data processing system having a line fetch mode of operation and a normal mode of operation, said memory system comprising:

an array of storage element units for storing a plurality of data elements in a predetermined pattern;
first, second, third, and fourth data element buses connected to said array of storage element units, each of said first and second buses for use in storing such data elements in the storage element units and each of said third and fourth buses for use in reading out such data elements stored in the storage element units;
means for storing a base storage element unit address and a stride value for a request, and data identifying the request as one of said line fetch and normal modes of operation;
and
controller means responsive to said data identifying the request as one of said line fetch and normal modes of operation and said stride value for controlling said array in said line fetch mode of operation to read out data elements at storage element unit addresses separated by said stride value using said third and fourth data element buses and for controlling said array in said normal mode for reading out data elements using said third and fourth data element buses and storing data elements using said first and second data element buses.

2 more elements

A method of operating a memory system for a data processing system in a line fetch mode of operation and a normal mode of operation, said memory system including an array of storage element units for storing a plurality of data elements in a predetermined pattern and first and second data element buses connected to said array of storage element units, each of said buses including means for reading out such data elements in storage element units, said method comprising the steps of:

storing a storage element unit base address and a stride value for a request and data identifying the request as one of said line fetch mode and said normal mode of operation;
if the request is for such a line fetch mode of operation, determining whether storage elements in said array at said base address and said base address plus said stride value are available and, if so, fetching corresponding data elements and selecting a next base address;
testing said next base address to determine if said next base address plus the stride value cross a boundary defined by a predetermined number of data elements and, if not, continuing to fetch data elements separated by said stride value until said boundary is crossed.

Dependencies are inferred from the claim text.

Stride enhancer for high speed memory accesses with line fetching mode and normal mode employing boundary crossing determination

Life of this patent

Stride enhancer for high speed memory accesses with line fetching mode and normal mode employing boundary crossing determination

Life of this patent

Abstract

Claims9