US 5,332,923 A · Semiconductor memory

Abstract

A semiconductor memory is provided which comprises memory cell regions disposed on a substrate, word lines which are connected respectively to the memory cells in the memory cell regions for controlling at least reading information from the memory cells, first bit lines which are formed in a first layer on the substrate and connected respectively to the memory cells for transmitting information, and second bit lines which are formed in a second layer and connected respectively to the memory cells for transmitting information, the second layer being formed on the substrate and electrically insulated from the first layer. The limitation of the layout upon the decrease of the bit line pitch can be eliminated, so that the reduction of the chip occupation area by shrinkage of areas between each adjacent memory cell regions can be realized. The first and second bit lines each is preferable to be patterned like stairs. The first and second bit lines are preferable to be disposed so as to go around the connecting area of the capacitor element for storing information and switching transistor in the memory cell.

Claims14

Dependent claims

A semiconductor memory having a folded bit-line structure, comprising:

a plurality of memory cell regions disposed on a semiconductor substrate;
a plurality of word lines which are connected respectively to memory cells in said memory cell regions,
said word lines being arranged along a first direction at given intervals;
a plurality of first bit lines which are formed in a first layer over said substrate and connected respectively to said memory cells, said first bit lines being arranged along a second direction at given intervals,
said second direction being substantially perpendicular to said first direction;
and
a plurality of second bit lines which are formed in a second layer over said first layer and connected respectively to said memory cells,
said second bit lines being arranged substantially along said second direction at given intervals, and
said second layer being electrically insulated from said first layer.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory

Life of this patent

Semiconductor memory

Life of this patent

Abstract

Claims14