Semiconductor memory NAND with wide space between selection lines

Abstract

A semiconductor memory device having a NAND-type memory cell structure for preventing the occurrence of an electrical bridge resulting from impurity particles generated during a manufacturing process. The space between the word-line whereto a Vcc voltage is applied and the string selection line whereto a Vss voltage is applied and a space between the string selection line of the string selection transistor and the word-line of the cell transistor adjacent to the string selection transistor, are wider than that between the word-lines so as to prevent early stand-by current failure caused by the special stand-by conditions of a NAND-type memory cell. Therefore, the occurrence of a polysilicon bridge between the word-line and the string selection line due to impurity particles generated during the manufacturing process is prevented. As a result, a defectively manufactured chip can be resurrected by the data correction means provided within the memory device.

Dependencies are inferred from the claim text.