Buried interconnect structure for semiconductor devices
AssigneeIntel Corporation
InventorJoseph Shappir
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorJoseph Shappir
Estimating the term…
An improved density semiconductor device having a novel buried interconnect is described. The buried interconnect electrically connects electrical device regions on a semiconductor substrate such that other structures may directly overlie the buried interconnect but not be electrically connected to the electrically conductive portions of the interconnect. The interconnect is composed of a buried conductor and conductive segments. The conductive segments are electrically joined to the buried conductor so as to form an electrical pathway. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. A nonconductive portion of selective poly-epi silicon is then formed over the buried conductor by oxidizing at least some of the selective poly-epi silicon layer. This nonconductive portion of the selective poly-epi silicon allows other structures to be formed over the buried conductor which are not in direct electrical contact with the buried interconnect. These other structures include elevated source/drain type structures, gates and silicidized or refractory metal local interconnects. These other structures may be selectively connected electrically to the conductive portions of the buried interconnect by the use of silicide segments or by the use of silicide segments connected electrically to titanium nitride pads. The conductive portion of the buried interconnect includes the buried conductor, and conductive segments which are formed by either silicon or silicide and which may include refractory metal pads. Silicide segments and titanium nitride pads are formed by depositing, annealing and etching a layer of refractory metal.
A buried interconnect on a semiconductor substrate, said substrate having a first conductive region, a nonconductive region, and a second conductive region, said first conductive region a being a diffusion region, comprising:
In a semiconductor device formed on a semiconductor substrate, said substrate having a plurality of device regions, said plurality of device regions including a first device and a second device region, said first device region including a diffusion region, said substrate further having a field oxide region and at least one gate, an improvement comprising:
Dependencies are inferred from the claim text.