Method of manufacturing a DRAM cell

A method of manufacturing a DRAM cell comprising the steps of:

• forming a word line having an oxide layer spacer on its side wall, on a silicon substrate;
• forming a first insulating layer on the entire silicon substrate;
• forming several contact holes by etching out some portions of the first insulating layer using contact masks for bit line and storage electrode;
• forming a contact plug by filling the contact holes with a conductive material;
• depositing a conducting layer fox bit line and a second insulating layer on the substrate including said first insulating layer and contact plug, and forming a second insulating layer pattern and bit line pattern on the contact plug for bit line by the etching process using a bit line mask;
• forming an insulating layer spaces on the side walls of the bit line pattern and the second insulating layer pattern;
• forming a third insulating layer over the entire substrate, and etching back until the underlying second insulating layer is exposed;
• forming a photoresist layer pattern for storage electrode contact mask on the third insulating layer;
• isotropically etching the third insulating layer that has been exposed to the contact plug for storage electrode, and removing the photoresist layer pattern for storage electrode contact mask;
• depositing a conducting layer for storage electrode over the entire substrate, and coating a photoresist layer over it;
• forming a storage electrode pattern by etching back the photoresist layer and conducting layer for storage electrode until the third insulating layer and the second insulating layer are exposed;
• removing the remaining photoresist layer, and wet etching out third insulating layer to expose the storage electrode;
• and
• forming a capacitor dielectric layer and plate electrode on top of the storage electrode.