Chemical/mechanical polishing for ULSI planarization

A method of forming a planar surface on a semiconductor wafer on which there is a first dielectric layer and a patterned first metal layer, comprising the steps of:

• forming a second dielectric layer with broad indentations over said first dielectric layer and said patterned first metal layer;
• forming a third dielectric layer over said second dielectric layer;
• forming a hard film layer over said third dielectric layer;
• patterning said third dielectric layer and said hard film layer to form polishing stop islands in said broad indentations;
• forming a fourth dielectric layer over said second dielectric layer and said polishing stop islands, to create a top surface for polishing, said fourth and second dielectric layers being less hard than said hard film layer;
• polishing said top surface in a vertical direction to remove portions of said top surface, until said top surface is co-planar with top of said polishing stop islands;
• and
• removing the remainder of said hard film layer to complete said planar surface.

A method of forming a semiconductor wafer having multiple levels of metallization with planar interlevel dielectric layers between each level of metallization, on which there is a first dielectric layer with broad indentations and a patterned first metal layer, comprising the steps of:

• forming a second dielectric layer over said first dielectric layer and said patterned first metal layer;
• forming a third dielectric layer over said second dielectric layer;
• forming a hard film layer over said third dielectric layer;
• patterning said third dielectric layer and said hard film layer to form polishing stop islands in the broad indentations;
• forming a fourth dielectric layer over said second dielectric layer and said polishing stop islands, to create a top surface for polishing, said fourth and second dielectric layers being less hard than said hard film layer;
• polishing said top surface in a vertical direction to remove portions of said top surface, until said top surface is co-planar with top of said polishing stop islands;
• and
• removing the remainder of said hard film layer to complete said planar surface and form an interlevel dielectric.