Semiconductor memory device having IO line pair to be equalized and divided into blocks and operating method thereof
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYoshinori Inoue
Life of this patent
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Abstract
In DRAM divided into plurality of blocks and operating on a block basis, each equalizing circuit is controlled such that release of equalization of an IO line pair is carried out only in a block having a memory cell from which data is to be read for data reading. Since a MOS transistor 40 provided between two IO lines constituting each IO line pair 2 for equalization of these lines and its release is not switched from on to off wastefully, current consumed for charge/discharge of a gate of the MOS transistor is considerably reduced compared to a conventional case.
Claims17
A dynamic random access memory, comprising:
- a plurality of blocks each including a plurality of memory cells arranged in a matrix of a plurality of rows and columns;
- a plurality of output line pairs provided corresponding to said plurality of blocks and each including first and second output liens serving to externally transmit complementary data signals from a corresponding block;
- selecting means for selecting any of said plurality of blocks in response to a row address signal;
- a plurality of equalizing means provided corresponding to said plurality of blocks and each equalizing the first and second output lines of the corresponding block;
- and
- equalizing control means for releasing equalization of the first and second output lines only of the block selected by said selecting means in response to a change of a column address signal in data reading.
A dynamic random access memory, comprising:
- a plurality of blocks each including a plurality of memory cells arranged in a matrix of a plurality of rows and columns;
- a plurality of output lines pairs provided corresponding to said plurality of blocks and each including first and second output lines for serving to externally transmit complementary data signals from a corresponding block;
- selecting means for selecting any of said plurality of blocks in response to a row address signal;
- a plurality of equalizing means provided corresponding to said plurality of blocks and each equalizing the first and second output liens of the corresponding block;
- detecting means for detecting a change of a column address signal;
- and
- equalization controlling means for enabling equalizing means provided corresponding to the block selected by said selecting means for a predetermined time after said change of the column address signal and then disabling it, and for enabling other equalizing means regardless of said detecting means, in data reading.
A dynamic random access memory, comprising:
- a plurality of memory cell blocks each including a plurality of emory cells arranged in a matrix of a plurality of rows and columns;
- a plurality of output line pairs provided corresponding to said plurality of memory cell blocks and each transmitting complementary data signals based on data read from a selected memory cell of a corresponding memory cell block;
- a plurality of equalizing means provided corresponding to said plurality of output line pairs and each equalizing a corresponding output line pair;
- and
- releasing means for releasing equalization of the output line in the block having the selected memory cell.
A method of operating a semiconductor memory device in data reading which comprises a plurality of blocks each including a plurality of memory cells arranged in a matrix of a plurality of rows and column, and a plurality of output line pairs provided corresponding to said plurality of blocks and each including first and second output lines serving to externally transmit complementary data signals from a corresponding block, comprising the steps of:
- selecting any of said plurality of blocks in response to a row address signal;
- detecting a change of a column address signal;
- equalizing first and second output lines provided corresponding to said selected block for a certain period of time after said change and releasing said equalized output lines;
- and
- equalizing the first and second output lines provided corresponding to each of the blocks except said selected block regardless of said detection.
Dependencies are inferred from the claim text.