Method of making non-volatile split gate EPROM memory cell and self-aligned field insulation

Process for fabricating a non-volatile split gate EPROM memory cell, the memory cell including a substrate with diffusions of source and drain separated by a channel area, a floating gate superimposed over a first part channel area and a control gate formed by a first and a second polysilicon strip, respectively, a cell gate oxide between said floating gate and said first part of the channel area, a transistor gate oxide between said control gate and a second part of the channel area, an interpoly oxide between said floating gate and said control gate and a layer of dielectric filler wherein said floating gate is aligned with the drain diffusion and said control gate is aligned with said floating gate and with the diffusions of the source and drain, said process comprising the steps of:

• defining parallel strips of field insulation and active area;
• implanting a cell channel in said semiconductor substrate;
• growing said cell gate oxide;
• depositing and doping of said first layer of polysilicon;
• defining the first polysilicon layer in first strips perpendicular to those of the field insulation;
• growing said transistor gate oxide and said interpoly oxide;
• depositing and doping of said second polysilicon layer;
• defining said second polysilicon layer in second strips parallel and partially superimposed over those of the first polysilicon layer;
• self-aligned etching of a multilayered structure comprising the second polysilicon layer, the transistor gate oxide, the interpoly oxide, the first polysilicon layer and the cell gate oxide up to the field insulation oxide;
• subsequent etching of said field oxide to uncover substrate strips;
• implanting said source and drain in the uncovered substrate strips;
• subsequent lateral sealing oxidation of the multilayered structure;
• and
• filling empty spaces between one cell and the next with said dielectric filler.