Method of making a six transistor static random access memory cell

A method of forming a static random access memory cell comprising the steps of:

• forming an active region lying within a semiconductor substrate having a first conductivity type and a primary surface, the active region lying adjacent to the primary surface and including a first segment, a second segment, and a third segment, wherein:
• the first segment has an adjacent end has a first length that generally extends a first distance in a first direction;
• the second segment has an adjacent end and has a second length that generally extends a second distance in the first direction;
• and
• the third segment has a first end and a second end and has a third length that generally extends in a second direction, which is generally perpendicular to the first direction, wherein the adjacent ends of the first and second segments lies near the first and second ends of the third segment, respectively;
• forming a first pass transistor, a second pass transistor, a first latch transistor, and a second latch transistor, wherein:
• each pass transistor includes a first source/drain region, a second source/drain region, a channel region, and a gate electrode;
• each latch transistor includes a source region, a drain region, a channel region, a gate dielectric layer, and a gate electrode;
• the gate dielectric layers of the latch transistors are formed simultaneously and the gate electrodes of the latch transistors are formed simultaneously;
• the channel region of the first pass transistor, the channel region of the first latch transistor, part of each of the first and second source/drain regions of the first pass transistor, and part of each of the source and drain regions of the first latch transistor lie within the first segment;
• the first source/drain region of the first pass transistor lies furthest from the adjacent end of the first segment and the source region of the first latch transistor lies closest to the adjacent end of the first segment;
• and
• the channel region of the second pass transistor, the channel region of the second latch transistor, part of each of the first and second source/drain regions of the second pass transistor, and part of each of the source and drain regions of the second latch transistor lie within the second segment;
• and
• the first source/drain region of the second pass transistor lies furthest from the adjacent end of the second segment and the source region of the second latch transistor lies the closest to the adjacent end of the second segment;
• and
• forming a first load transistor and a second load transistor within a layer having a fourth segment, a fifth segment, and a sixth segment, wherein:
• the fourth segment has an adjacent end, has a fourth length that generally extends a fourth distance in the first direction, and lies over the first segment, wherein the fourth distance is shorter than the first distance;
• the fifth segment has an adjacent end, has a fifth length that generally extends a fifth distance in the first direction, and lies over the second segment, wherein the fifth distance is shorter than the second distance;
• the sixth segment has a first end and a second end, has a sixth length that generally extends in the second direction, and lies over the third segment, wherein the adjacent ends of the fourth and fifth segments lie near the first and seconds ends of the sixth segment, respectively;
• the gate electrode of the first latch transistor also acts as a gate electrode for the first load transistor and the gate electrode of the second latch transistor also acts as a gate electrode for the second load transistor;
• each load transistor includes a source region, a drain region, and a channel region, wherein the channel region
• has a drain-side edge lying at the drain region of its load transistor;
• has a drain offset region, which is that portion of the channel region of its load transistors lying immediately adjacent to the drain-side edge and does not overlie the gate electrode of its load transistor;
• and does not have a source offset region;
• the source, drain, and channel regions of the first load transistor lie within the fourth segment and the source region of the first load transistor lies nearest to the adjacent end of the fourth segment compared to the drain and channel regions of the first load transistor;
• and
• the source, drain, and channel regions of the second load transistor lie within the fifth segment and the source region of the second load transistor lies nearest to the adjacent end of the fifth segment compared to the drain and channel regions of the second load transistor,
• wherein the memory cell is configured such that:
• the first source/drain region of the first pass transistor is electrically connected to a first bit line, the first source/drain region of the second pass transistor is electrically connected to a second bit line;
• the gate electrodes of the pass transistors are part of a word line;
• the source regions of the latch transistors are electrically connected to one another;
• and
• the source regions of the load transistors are electrically connected to one another.