Method of constructing a reduced size highly integrated static random access memory with double vertical channel structure

A method of making a static random access memory comprising the steps of:

• forming, on a substrate of a first conductivity type, an impurity diffusion region of a second conductivity type functioning as a first source/drain region;
• forming a first layer of the first conductivity type, on the substrate;
• forming a second impurity diffusion region of the second conductivity type, on the first layer;
• forming a second layer of the first conductivity type, on the first layer;
• forming a third impurity diffusion region of the second conductivity type, on the second layer, such that the center of the third impurity diffusion region is located on a vertical line passing the center of the first impurity diffusion region;
• forming a first trench extending from the surface of the third impurity diffusion region to the second impurity diffusion region and having a width less than that of the third impurity diffusion region, based on the center of the third impurity diffusion region so that respective remaining portions of the third impurity diffusion region and the second layer at opposite sides of the first trench become a second source/drain region and a first vertical channel region;
• forming first gate electrodes at opposite sides of the first trench, respectively, and forming a first insulating region around each first gate electrode, the first insulating region functioning to insulate electrically the first gate electrode from other parts;
• forming a second trench extending from the remaining bottom portion of the first trench to the surface of the first impurity diffusion region and having a width corresponding to the width of the remaining bottom portion of the first trench so that respective remaining portions of the second impurity diffusion region and the first layer at opposite sides of the second trench become a third source/drain region and a second vertical channel region;
• forming second gate electrodes at opposite sides of the second trench, respectively, and forming a second insulating region around each second gate electrode, the second insulating region functioning to insulate electrically the second gate electrode from other parts;
• forming a ground electrode at a portion of the second trench defined between second insulating regions, the portion corresponding to the remaining center portion of the second trench;
• forming a third trench at a portion of the second layer corresponding to a region defined between adjacent memory cells;
• and
• forming third insulating regions and load resistors being in contact with the first layer, at opposite sides of the third trench, respectively.