US 5,330,924 A · Method of making 0.6 micrometer word line pitch ROM cell by 0.6 micrometer technology

Abstract

A cost-effective and manufacturable method for producing ROM integrated circuits with closely-spaced self-aligned conductive lines, on the order of 0.3 micrometers apart, is described. Parallel, conductive semiconductor device structures are formed in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A first conductive polysilicon layer is formed over the insulating layer. The first conductive polysilicon layer is patterned to form first polysilicon conductor lines which are parallel to each other, and orthogonal to the parallel, conductive semiconductor device structures. A first silicon oxide layer is formed on and between the first polysilicon conductor lines. The first silicon oxide layer is anisotropically etched to produce sidewall structures on the first polysilicon conductor lines. A second silicon oxide layer is formed on and between the first polysilicon conductor lines. A second conductive polysilicon layer is formed over the first polysilicon conductor lines and in openings between the first polysilicon conductor lines. The second conductive polysilicon layer is etched back to form second polysilicon conductor lines, parallel to, between and self-aligned with the first polysilicon conductor lines, and separated from the first polysilicon conductor lines by width of the sidewall structures.

Claims31

Dependent claims

A method of manufacturing closely spaced self-aligned polysilicon conductor lines in a ROM integrated circuit having cell and peripheral regions, comprising the steps of:

forming parallel, conductive semiconductor device structures in a semiconductor substrate;
forming an insulating layer over said semiconductor substrate;
forming a first conductive polysilicon layer over said insulating layer;
patterning said first conductive polysilicon layer to form first polysilicon conductor lines which are parallel to each other, and orthogonal to said parallel, conductive semiconductor device structures;
forming a first silicon oxide layer on and between said first polysilicon conductor lines;
anisotropically etching said first silicon oxide layer to produce sidewall structures on said first polysilicon conductor lines;
forming a second silicon oxide layer on and between said first polysilicon conductor lines;
forming a second conductive polysilicon layer over said first polysilicon conductor lines and in openings between said first polysilicon conductor lines;
and
etching back said second conductive polysilicon layer to form second polysilicon conductor lines, parallel to, between and self-aligned with said first polysilicon conductor lines, and separated from said first polysilicon conductor lines by the width of said sidewall structures.

7 more elements

A method of manufacturing a ROM integrated circuit, having cell and peripheral regions, using closely spaced self-aligned polysilicon conductor lines, comprising the steps of:

forming parallel buried N conductivity type regions in a semiconductor substrate;
forming an insulating layer over said semiconductor substrate;
forming a first conductive polysilicon layer over said insulating layer;
patterning said first conductive polysilicon layer to form first polysilicon conductor lines which are parallel to each other, and orthogonal to said parallel, buried N+ regions;
forming a first silicon oxide layer on and between said first polysilicon conductor lines;
anisotropically etching said first silicon oxide layer to produce sidewall structures on said first polysilicon conductor lines;
forming a second silicon oxide layer on and between said first polysilicon conductor lines;
forming a second conductive polysilicon layer over said first polysilicon conductor lines and in openings between said first polysilicon conductor lines;
etching back said second conductive polysilicon layer to form second polysilicon conductor lines, parallel to, between and self-aligned with said first polysilicon conductor lines, and separated from said first polysilicon conductor lines by the width of said sidewall structures;
and
electrically connecting said first and second polysilicon conductor lines and said buried N conductivity type regions to complete the ROM integrated circuit.

8 more elements

Dependencies are inferred from the claim text.

Method of making 0.6 micrometer word line pitch ROM cell by 0.6 micrometer technology

Life of this patent

Method of making 0.6 micrometer word line pitch ROM cell by 0.6 micrometer technology

Life of this patent

Abstract

Claims31