Integrated circuit test reticle and alignment mark optimization method

A method of using a test reticle to align integrated circuit process layers, said method comprising the steps of:

• generating a test reticle having a pattern including a plurality of alignment mark groups, each of said groups including a particular type of alignment mark in one or more predetermined sizes, and one or more registration structures;
• determining an initial expected range of said predetermined alignment mark sizes suitable for a particular application;
• applying said pattern of said test reticle to a process layer of one or more test wafers;
• processing said test wafers having said pattern of said test reticle thereon through one or more additional processing steps;
• measuring alignment signals produced by scanning alignment marks having a size in said initial expected range;
• quantifying said alignment signals using a measure of alignment signal quality;
• and
• fitting said quantified alignment signals to a statistical model in order to determine one or more optimized alignment mark sizes which result in an acceptable level of said alignment signal quality.

A method of using a reticle to align integrated circuit process layers, said method comprising the steps of:

• generating a test reticle having a pattern including a plurality of alignment mark groups, each of said groups including a particular type of alignment mark in one or more predetermined sizes, and one or more registration structures;
• applying said pattern of said test reticle to a process layer of one or more test wafers;
• processing said test wafers having said pattern of said test reticle thereon through one or more additional processing steps;
• determining from said test wafers one or more optimized alignment mark sizes which result in an acceptable level of alignment signal quality;
• and
• applying at least one alignment mark of said optimized alignment mark size to one or more product wafers.