Test chip for semiconductor fault analysis

Abstract

A semiconductor test chip for use in semiconductor fabrication fault analysis, comprises an n.times.m array of transmission gate cells arranged such that within a given row respective strips of conductive material of a first type form common source and drain electrodes for the transistors of the row, the sources and drains of each row being independent, and within a column strips of conductive material of a second type form common gate electrodes such that each column of transistors can be turned on independently. An input circuit permits a predetermined bit pattern to be selectively applied to the inputs of the rows of transmission gate cells. A demultiplexer including output transmission gates is connected to respective outputs of the rows of the array for selectively addressing the output of each row of transmission gate cells. A centre-pulled operational amplifier is connected to the outputs of said output transmission gate cells, and the output of the operational amplifier is coded according a logic scheme having three levels. Another demultiplexer is provided for selectively turning on each column of transmission gate cells. In this way, the physical nature and location of defects in the chip can be determined from said multi-level coded output. The results are useful for characterizing process yields and reliability, They can also be used for high level yield modelling.

Dependencies are inferred from the claim text.