Semiconductor device and preparing method therefor
AssigneeSharp Kabushiki Kaisha
InventorHitoshi Aoki
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Abstract
A semiconductor device which comprises a semiconductive substrate having thereon a plurality of source/drain regions arranged parallel to each other and a plurality of gate electrodes which extend perpendicularly to and above the source/drain regions through a gate oxide film, wherein at least one of a specific pair of source and drain regions corresponding to any desired at least one of the gate electrodes is provided with an offsetting stepped portion extending in the direction of depth of the substrate, and the offsetting stepped portion is filled up with an insulating film for filling up the stepped portion, so that the specific source/drain region provided with the offsetting stepped portion is disposed with respect to the corresponding gate electrode through a step of the offsetting stepped portion.
Claims11
A memory cell array providing a plurality of memory cells which comprises:
- a semiconductive substrate having thereon a plurality of source/drain regions arranged parallel to each other;
- a plurality of gate electrodes which extend perpendicularly to and above the source/drain regions through a gate oxide film;
- and
- a channel region formed in the semiconductor substrate between source/drain regions and just below the gate electrode;
- wherein a memory cell of the array is formed at a crossing of a pair of the source/drain regions and one of the gate electrodes, either source/drain region of the memory cell having a side which is spaced from an upper surface of the substrate to form an offsetting stepped portion between the source/drain region and the channel region, and the offsetting stepped portion is filled up with an insulating film for filling up the stepped portion, so that the specific source/drain region provided with the offsetting stepped portion is disposed with respect to the corresponding gate electrode through the offsetting stepped portion and the gate electrode extends over the pair of the source/drain regions and over the offsetting stepped portion.
A two bit memory cell comprising:
- a semiconductive substrate having an upper surface, the substrate having therein a pair of source/drain regions arranged parallel to each other;
- a gate electrode which extends perpendicularly to and above the source/drain regions;
- and
- a channel region formed in the semiconductor substrate between source/drain regions and just below the gate electrode;
- wherein the memory cell is formed at a crossing of the pair of the source/drain regions and the gate electrode, at least one of the source/drain regions having a side which is spaced from the upper surface of the substrate in such a manner that electrical conduction occurs between the pair of source/drain regions when a voltage is applied to the recessed source/drain region for operating the recessed source/drain region as a drain, but wherein electrical conduction does not occur between the pair of source/drain regions when the recessed source/drain region is operated as a source;
- and
- wherein the gate electrode extends over the pair of the source/drain regions.
A two bit memory cell comprising:
- a semiconductive substrate having an upper surface, the substrate having therein a pair of source/drain regions arranged parallel to each other;
- a gate electrode which extends perpendicularly to and above the source/drain regions;
- and
- a channel region formed in the semiconductor substrate between source/drain regions and just below the gate electrode;
- wherein the memory cell is formed at a crossing of a pair of the source/drain regions and the gate electrodes, a first of the source/drain regions having a side which is spaced from the upper surface of the substrate in such a manner that electrical conduction does not occur between the pair of source/drain regions when the first source/drain region is operated as a source;
- and
- wherein the gate electrode extends over the pair of the source/drain regions.
Dependencies are inferred from the claim text.