Heterojunction bipolar transistor and its integration method

A heterojunction bipolar transistor comprising:

• (a) an InP substrate and
• (b) an epitaxial layered structure on said InP substrate, said epitaxial layered structure including
• (c) a collector or emitter layer of p type In.sub.x Al.sub.1-x As lattice matched to said InP substrate,
• (d) a first spacer layer of p type In.sub.x Ga.sub.1-x As
• (e) a base layer of n type In.sub.x Ga.sub.1-x As and
• (f) a second spacer layer of p type In.sub.x Ga.sub.1-x As
• (g) an emitter or collector layer of p type In.sub.x Al.sub.1-x As lattice matched to the InP substrate,
• said heterojunction bipolar transistor further comprising:
• (h) an external base region comprising an n type In.sub.x Ga.sub.1-x As layer contiguous to said base layer of n type In.sub.x Ga.sub.1-x As and an n type In.sub.x Al.sub.1-x As layer contiguous to said emitter or collector layer of p type In.sub.x Al.sub.1-x As, said n type In.sub.x Al.sub.1-x As layer being formed by introduction of an n type impurity into said p type In.sub.x Al.sub.l-x As layer beneath said base layer and resulting conversion of the conductivity type of the In.sub.x Al.sub.l-x As layer from p type to n type.

An integrated semiconductor device comprising:

• (a) a collector top type pnp heterojunction bipolar transistor (HBT) and
• (b) a lateral npn bipolar transistor (BT), wherein said collector top type pnp HBT comprises:
• (c) an InP substrate and
• (d) an epitaxial layered structure on said InP substrate, said epitaxial layered structure including
• (e) an emitter layer of p type In.sub.x Al.sub.l-x As matching in lattice at least with said InP substrate,
• (f) a base layer of n type In.sub.x Ga.sub.l-x As and
• (g) a collector layer of p type In.sub.x Ga.sub.l-x As or p type In.sub.x Al.sub.l-x As lattice matched to the InP substrate, said collector top type pnp heterojunction bipolar transistor (HBT) further comprising:
• (h) an external base region comprising an n type In.sub.x Ga.sub.l-x As layer contiguous to said base layer of n type In.sub.x Ga.sub.l-x As and an n type In.sub.x Al.sub.l-x As layer contiguous to said emitter or collector layer of p type In.sub.x Al.sub.l-x As, said n type In.sub.x Al.sub.l-x As layer being formed by introduction of an n type impurity into said p type In.sub.x Al.sub.l-x As layer beneath said base layer and resulting conversion of the conductivity type of the n.sub.x Al.sub.l-x As layer from p type to n type,
• and wherein the lateral npn BT where electrons run laterally, comprises
• (i) a base region of p type In.sub.x Al.sub.l-x As interposed between said two n type In.sub.x Al.sub.l-x As regions, and
• (j) a collector or emitter formed of n type In.sub.x Al.sub.l-x As.

A heterojunction bipolar transistor comprising:

• (a) an InP substrate and
• (b) an epitaxial layered structure on said InP substrate, said epitaxial layered structure including
• (c) a collector or emitter layer of p type In.sub.x Al.sub.l-x As,
• (d) a base layer of n type In.sub.x Ga.sub.l-x As and
• (e) an emitter or collector layer of p type In.sub.x Al.sub.l-x As, said heterojunction bipolar transistor further comprising:
• (f) an external base region comprising an n type In.sub.x Ga.sub.l-x As layer contiguous to said base layer of n type In.sub.x Ga.sub.l-x As and an n type In.sub.x Al.sub.l-x As layer contiguous to said emitter or collector layer of p type In.sub.x Al.sub.l-x As, said n type In.sub.x Al.sub.l-x As layer being formed by introduction of an n type impurity into said p type In.sub.x Al.sub.l-x As layer beneath said base layer and resulting conversion of the conductivity type of the In.sub.x Al.sub.l-x As layer from p type to n type.

A symmetric structure PnP type heterojunction bipolar transistor comprising:

• (a) an In.sub.x Al.sub.l-x As/In.sub.x Ga.sub.l-x As PnP type system lattice matched to an InP substrate,
• (b) an intrinsic base-emitter diode formed in said In.sub.x Al.sub.l-x As/In.sub.x Ga.sub.l-x As PnP type system;
• (c) a base-emitter diode formed in a wide-gap semiconductor material by introducing into an external base region an n type impurity, thereby forming said external base region by an n type In.sub.x Ga.sub.l-x As layer and an n type In.sub.x Al.sub.l-x As layer, said n type In.sub.x Al.sub.l-x As layer being formed by introduction of said n type impurity into said p type In.sub.x Al.sub.l-x As layer beneath the intrinsic base-emitter diode and resulting conversion of the conductivity type of the In.sub.x Al.sub.l-x As layer from p type to n type,
• wherein the built-in voltage in said external base-emitter diode formed in the wide-gap semiconductor material is substantially higher than the built-in voltage of the intrinsic base-emitter diode.

A heterojunction bipolar transistor comprising:

• (a) a semi-insulating InP substrate;
• (b) a sequential stack disposed on said InP substrate;
• said sequential stack including
• (c) a first contact layer of p type In.sub.0.53 Ga.sub.0.47 As of a thickness of 500 nm including a p type impurity of 4.times.10.sup.19 /cm.sup.3,
• (d) a collector or emitter layer of p type In.sub.0.53 Al.sub.0.47 As of a thickness of 200 nm including a p type impurity of 2.times.10.sup.17 /cm.sup.3,
• (e) a first spacer layer of p type In.sub.0.53 Ga.sub.0.47 As of a thickness of 30 nm including a p type impurity of 2.times.10.sup.17 /cm.sup.3,
• (f) a base layer of n type In.sub.0.53 Ga.sub.0.47 As of a thickness of 15 nm including a n type impurity of 1.times.10.sup.19 /cm.sup.3,
• (g) a second spacer layer of p type In.sub.0.53 Ga.sub.0.47 As of a thickness of 30 nm including a p type impurity of 2.times.10.sup.17 /cm.sup.3,
• (h) a collector or emitter layer of p type In.sub.0.53 Ga.sub.0.47 As of a thickness of 200 nm including a p type impurity of 2.times.10.sup.17 /cm.sup.3, and
• (i) a second contact layer of p type In.sub.0.53 Ga.sub.0.47 As of a thickness of 100 nm including a p type impurity of 4.times.10.sup.19 /cm.sup.3.

A ternary compound heterojunction bipolar transistor comprising:

• (a) a substrate;
• (b) a collector or emitter layer of a first compound having a first conductivity type, formed on said substrate;
• (c) a first spacer layer of a second compound doped with a first conductivity type dopant, formed on said collector or emitter layer;
• (d) a base layer of the second compound having a second conductivity type, formed on said first spacer layer;
• (e) a second spacer layer of the second compound doped with the first conductivity type dopant, formed on said base layer;
• (f) an emitter or collector layer of the first compound having the first conductivity type, formed on said second spacer layer,
• wherein said base layer is sandwiched between the first and second spacer layers doped with the opposite conductivity type dopant and the resulting heterojunction bipolar transistor is of a symmetric structure operable in either emitter top mode or collector top mode.