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US 5,329,143 AGranted
ESD protection circuit
AssigneeSGS-Thomson Microelectronics S.A.
InventorsTsiu C. Chan, David S. Culver
Life of this patent
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Abstract
An ESD protection circuit and structure for integrated circuit devices uses a lateral NPN transistor to provide a low resistance discharge path for ESD transient voltages. A preferred structure also includes a modification to an N-channel output drive transistor to eliminate the parasitic bipolar transistor that induces snapback.
Claims17
An electrostatic discharge protection circuit for a semiconductor integrated circuit, comprising:
- an input/output bonding pad;
- an output driver connected to said bonding pad;
- a bipolar transistor connected to said bonding pad, wherein a high voltage on said bonding pad causes said bipolar transistor to turn on and shunt current from said bonding pad to ground;
- and
- a heavily doped guard ring partially surrounding said bipolar transistor, wherein said guard ring has a gap located adjacent an emitter of said bipolar transistor, and wherein the gap is positioned to control a voltage at which said bipolar transistor turns on.
2 more elements
An output protection circuit for a CMOS device, comprising:
- a p-type well region in a semiconductor substrate;
- a heavily doped guard ring in said well, said heavily doped guard ring connected to a device ground;
- a first n-type region in said well near said guard ring, said first n-type region also connected to the device ground;
- a second n-type region in said well near said first n-type region;
- a bond pad connected to said second n-type region;
- and
- an N-channel transistor i said well, having a drain connected to said bond pad and a source, wherein the source has a plurality of heavily doped p-type regions within it contacting said well, wherein such p-type regions and the source are connected to the device ground;
- wherein said first n-type region and said guard ring are spaced apart a sufficient distance that ESD current flow within the well region generates a voltage differential between said first n-type region and said guard ring sufficient to turn on a lateral npn transistor, and wherein said first n-type region, said guard ring, and said second n-type region function respectively as an emitter, base, and collector of a lateral npn transistor which turns on and shunts current to device ground when a high voltage is present on said bond pad.
5 more elements
An output protection circuit for a CMOS device, comprising:
- a p-type well region in a semiconductor substrate;
- a heavily doped guard ring in said well, said heavily doped guard ring connected to a device ground;
- a first n-type region in said well near said guard ring, said first n-type region also connected to the device ground;
- a second n-type region in said well near said first n-type region;
- a bond pad connected to said second n-type region;
- and
- an N-channel transistor in said well, having a drain connected to said bond pad and a source connected to the device ground;
- wherein said first n-type region and said guard ring are spaced apart a sufficient distance that ESD current flow within the well region generates a voltage differential between said first n-type region and said guard ring sufficient to turn on a lateral npn transistor, wherein said first n-type region, said guard ring, and said second n-type region function respectively as an emitter, base, and collector of a lateral npn transistor which turns on and shunts current to device ground when a high voltage is present on said bond pad, and wherein said guard ring includes a gap therein in a portion nearest to said first n-type region.
5 more elements
Dependencies are inferred from the claim text.